Logic probe using ATTINY26

A Logic Probe with the usual LEDs and sound output based on an ATTINY26.
My entry to the 1k challenge.

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The logic probe uses the ADC to detect proper logic levels with ~10k samples per
second. Short pulses or high frequency changes may not be detected this way.
Therefore level changes are detected by the INT0 input in toggle mode. At 8MHz
pulses longer than 125ns can be detected.

3 LEDs signal high and low logic levels and detected level changes or pulses.
The pulse LED stays lit for 100ms after the last pulse edge was detected.

A magnetic transducer makes logic levels and level changes or pulses audible.
A steady low = 650 Hz, a steady high = 1750 Hz, a level change only = 1100Hz.
A low with high pulses warbles with 650 Hz and 1100 Hz. A high with low pulses
warbles with 1750 Hz and 1100 Hz.

The project files are also available at


The logic probe is intended to be built on a perfboard, so there is no board layout.

I chose an ATTINY26 for this project simply because I had one. However, it should be possible to port the project to smaller or newer ATTINYs if needed. The AVR must have

  • an analog to digital converter
  • an external interrupt pin configurable to detect both edges
  • a timer with output compare match toggling an output pin
  • a second more simplistic timer to generate a timer tick
  • 5 additional I/O pins for 3 LEDs, 1 switch and 1 output to precharge the probe

The fuses of the microcontroller should be set to run on the 8 MHz internal oscillator.

The resistor network R8, R9 & R10 precharge the probe through R1 with a voltage suitable to detect an open circuit. The voltage to signal an undefined logic level is 1.4V for TTL and 2.5V for CMOS. Port A Pin 6 drives R9 high in CMOS-mode, hi-Z in TTL-mode.

The LEDs should be low current types as their resistors allow 5mA at 5V per LED. It is up to you to choose the colors you want to signal high, low or pulse. The sound output device is a magnetic transducer with 40 Ohms impedance. If you have to replace the BJM 05 with a different type, it should not have a lower impedance. Otherwise you might need to add an amplifier.

The switch S1.1 disconnects the speaker if the sound annoys you or your co-workers. The switch S1.2 selects TTL-mode if on, CMOS-mode if off. If you do not want TTL-mode just leave port A pin 7 disconnected. At the same time you can leave pin 6 on the same port also disconnected and bridge R10 (connect R9 directly to Vcc).

The Logic Probe takes its power from the circuit under test. Be careful not to operate the microcontroller outside of its specified operating voltage. Do not reverse Vcc and Ground leads!


For all my AVR assembler projects I use an include with macros to allow me to better structure programs with IF-ELSE-END and DO-EXIT-LOOP blocks. I have written the macros in 2010, they are called "Structured Assembly Macros" and live in "".

The program is very simple as it does not use any interrupts or subroutine calls. I still load the stack pointer though, because it is good practice to do so. The reset code then goes on to initialize

  • the oscillator calibration register
  • timer 0 as an 8ms tick timer
  • timer 1 as the frequency generator for the sound
  • LED pins, perform a 1 second all on to verify LEDs are O.K.
  • the ADC to take its reference voltage from Vcc, output 8 bits to the ADC high register, use ADC9 (port B pin 6) as input, use 125kHz as ADC clock and start free run mode
  • to set the INTF0 flag on both edges detected on INT0 (port B pin 6)
  • registers for sample counts, edge timer, current logic state frequency

The main program loop consists of 3 major blocks, AD conversion complete, 8ms timer tick and signal edge detected.

The ADC block first decides which levels apply by checking the CMOS/TTL switch. The ADC result sets the high or low LED and counts the samples from last 8 ms timer tick. Finally the probe precharge voltage level is set.

The 8 ms timer tick block first checks whether the 100 ms pulse LED on timer is expired. Then the sample counts and pulse timer determine if the sound should be enabled and which frequency should be used. The last frequency is verified with the current selection and if it is the same the pulse timer gets priority. This causes the sound to warble when a pulse is detected with at least one valid logic level.

In the last block the external interrupt flag is checked and if set turns on the pulse LED and loads or reloads the pulse LED on timer with ~ 100 ms.


The ADC takes almost 10.000 samples per second when running at 125kHz in free running mode. In the first of the 13 cycles of an AD conversion the sample and hold capacitor is charged from the ADC input pin. Whatever mix of levels is present during that cycle is averaged and then converted. A cycle is 8 µs at 125 kHz. However, only the last 5 µs of the sample cycle are relevant...

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Assembler listing

lss - 13.94 kB - 12/22/2016 at 15:30



Assembler source

asm - 7.76 kB - 12/22/2016 at 15:30



Object code

hex - 652.00 bytes - 12/22/2016 at 15:30


Structured assembly macros

inc - 11.66 kB - 12/21/2016 at 18:12


  • 1 × IC1: ATTINY26 microcontroller
  • 1 × SP1: BJM 05, Z=40 Ohms 5V magnetic transducer
  • 3 × LED1, LED2, LED3: low current LED your choice of red, green or yellow
  • 1 × S1: DIP switch 2 switches or jumper bridges
  • 2 × C1, C2: 100nF capacitor foil or ceramic >5V

View all 12 components

  • Breadboard adapter

    Klaus Dormann01/04/2017 at 10:02 0 comments

    I built a breadboard adapter on a perfboard yesterday. It has the logic probe and a clamp to a breadboard built by a small upside down section of perfboard with 11 x 4 holes. The clamp is fixed to the logic probe by 4 wires through both perfboards and soldering them on both sides. 4 pins hook to signal columns of the breadboard while 2 pins on each side connect to the power rail rows. I always use the convention of having ground on the inside rail and Vcc on the outside rail. The adapter can also be used to bridge power from one half of the power rail to the other.

    A connector is provided at pin 9 of the ATTiny26 to plug in the probe. The DIP-switches are replaced with jumpers. The pictures show sound on, CMOS level. The LEDs are green for low, red for high and yellow for pulse.

  • ADC Calculations

    Klaus Dormann12/24/2016 at 11:42 0 comments

    You may have noticed that the ADC is used in 8-bit mode as the ADLAR bit (ADC left adjust result) is set in ADMUX. At the same time we only use ADCH to determine the voltage thresholds. The reference voltage is set to Vcc. So we get 0 for ground and 255 for Vcc. Now we need to use the rule of three (also called the rule of proportion) to find the ADCH values for a certain percentage or voltage.

    For CMOS the voltages are defined as <= 30% Vcc for low, >= 70% for high.

    • ADCth = ADCHmax * Vth% / 100%
    • ADClow = 255 * 30 / 100 = 76.5
    • ADChigh = 255 * 70 / 100 = 178,5

    Since we can only compare an integer with ADCH we need to cut off the result to an integer. The compare results are based on the carry flag of the compare. 0 = same or higher, 1 = lower. As we want to compare the lower threshold to be lower or equal we need to elevate the lower threshold by 1. I used ADClow = 77 and ADChigh = 178.

    For TTL the voltages are defined as Vcc = 5V, Vlow = 0.8V and Vhigh = 2V

    • ADCth = ADCHmax * Vth / Vcc
    • ADClow = 255 * 0.8 / 5 = 40.8
    • ADChigh = 255 * 2 / 5 = 102

    Again we need to only use the integer part and elevate the lower threshold by 1: ADClow = 41 and ADChigh = 102

    Why to cut off and not to round? Remember, the 2 least significant bits of the ADC result are also cut off, so an ADC result of 76.75 is still lower than 77. If we would have rounded 76.5 + 1 we would compare to 78 and that would actually be less accurate.

  • 1k challenge

    Klaus Dormann12/23/2016 at 11:37 0 comments

    The size of the binary code from the bottom of the listing (Logic_Probe.lss):

    "ATtiny26" memory use summary [bytes]:
    Segment   Begin    End      Code   Data   Used    Size   Use%
    [.cseg] 0x000000 0x0000dc    220      0    220    2048  10.7%
    [.dseg] 0x000060 0x000060      0      0      0     128   0.0%
    [.eseg] 0x000000 0x000000      0      0      0     128   0.0%
    I used Atmel Studio 6.1 to assemble the source code.

  • TTL open level

    Klaus Dormann12/22/2016 at 13:21 0 comments

    just noticed that the input thresholds for TTL are not compatible with the resitor network on the probe pin. >= 2.0V is TTL high but the resistors source ~ 2.5V compatible with CMOS thresholds. One more resistor and an output pin of the ATTINY should do the trick.

    update: The Problem was fixed by a redesign of the probe precharge resistor network and bypassing the resistor connected to Vcc in CMOS mode.

View all 4 project logs

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