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Gigatron: the TTL microcomputer

"Just because":
The microcomputer that runs without a microprocessor

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In 1975 Wozniak famously designed the Breakout arcade game out of 44 simple chips, without using a microprocessor, simply because those weren't available to him at the time. When one year later the MOS 6502 and Zilog Z80 were launched, his Apple 1 started the microcomputer revolution. The debate still rages about which processor was the better one. But more interesting is to investigate if these devices were really necessary for the personal computer revolution at all: what would have happened if they had never appeared?

Update: For news about the kit version of this project, check out the pre-announcement in the blog: https://hackaday.io/project/20781-gigatron-the-ttl-microcomputer/log/71293-gigatron-the-ttl-co

History followed one path
There were many other ways
It will always be like that

Can fewer than 40 old-skool TTL chips implement a multi-MHz 64 color computer?

This project started as an exploration of what you can build from 30-40 simple logic chips. It has turned into a general purpose 8-bit microcomputer without any microprocessor driving it. I initially designed this on a breadboard, but this summer I have converted it all to a small PCB. It has VGA-compatible 60 Hz video in 64 colors and can display full-screen images, scroll them and play sound. Soon it will be running games like Pac Man and Space Invaders. But just for fun, I'll keep everything compatible with the breadboard design.

This is what we have now:
• 8-bits system built out of 1970s TTL chips (74LS)
• 34 TTL ICs, or 930 logic gates, for the CPU proper
• No microcontroller and no complex chips (such as the 74181 ALU)
• Only simple ICs, such as AND/OR, 4-bit adders, multiplexers, registers and so on
• 6.3 MHz. Might be pushed to 8 MHz
• 32kB 70ns RAM
• Harvard architecture with EPROM for program/data
• Operates on 2.5W, or below 0.5W for the 74HCT version
• RISC with pipelining:  1 instructions per clock (sometimes 2...)
• Instruction decoding with diodes
• Nice instruction set: ADD/SUB/AND/OR/XOR, conditional jumps, many useful addressing modes
• 60Hz 64 color VGA and 4 sound channels bit-banged from software
• Designed and built on a solderless breadboard in 6 weeks

The build has become a contradiction of itself. Every hardware function is essentially software-defined: video, audio and I/O are all handled by software. Video at the pixel level. Audio at the sample level, in 4 channels. Even the applications themselves will be running in an interpreter (aka a virtual processor). Yet there is no microprocessor that runs any of that. And not only does it work, the board is smaller and faster than the microcomputers of the day, including the first IBM PC. Having no microprocessor might have been better than having any of the time :-)

Check the videos for the current capabilities. The HaD blog section has the full story in all detail, so don't miss that if you're interested.

Some concepts to ponder about before starting

  1. How many bits? 4, 8, 16, 32, ...
  2. Software-generated video or hardwired?
  3. Harvard or Von Neumann architecture?
  4. Single cycle or multi cycle? Pipelining?
  5. ALU chips or not?
  6. Sliced ALU or full width?

A rule of thumb is that a minimalistic four bit system can be done in 10 chips, an eight bitter needs no more than 20 chips and going to 16 bits roughly doubles that again. Not all units double in chip count, but by extending the buses you will also have need for more addressing modes for it all to make sense. For example, a four bitter might work fine with a 256 word memory and absolute addressing, but with larger memories you'll need ways to construct addresses dynamically. Also, add more chips if extra functionality is required, such as high speed, a stack pointer, interrupts, a custom ALU or video.

Simplest possible concept

One concept, probably the simplest, is to replace the TrinketPro from the earlier breadboard VGA from TTL and SRAM with a minimalistic 4-bit TTL CPU. We will then get a working system with around 25 chips, or about 30 if we make a custom ALU. It will indeed be good enough for Pac Man and Space Invaders, but that will then also be the limit: no chance at all to have any fast scrolling, fast color changes, smooth moving objects, large objects, etcetera. Upgrading the CPU part to 8-bits won't bring much, because there will still be a communication bottleneck between the two parts. For any more exciting video we will need more complexity in the video part. If we do both, we certainly end up with more than 40 chips. It is absolutely interesting to try out this 25 chip concept (I would do it with a 74'181 ALU chip), because...

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theloop.asm

Disassembly of ROM file

asm - 560.83 kB - 10/19/2017 at 20:10

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theloop.2.rom

Object ROM file for 27C1024

rom - 42.65 kB - 10/19/2017 at 20:10

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Scroller64.rgb

Scroll text

x-rgb - 8.25 kB - 10/19/2017 at 20:07

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rrggbb-Selfie-160x120.rgb

Photo of breadboard version

x-rgb - 56.25 kB - 10/19/2017 at 20:07

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theloop.py

Operating system showing core capabilities

x-python-script - 24.12 kB - 10/19/2017 at 20:06

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  • Wrapping up the software for ROM v1

    Marcel van Kervinck7 days ago 2 comments

    The software to be included with the kit release later this month is nearly done. Just in time as we're now also waiting for the last parts shipment to arrive, expected in two weeks. When those are good we know if we can meet our target selling price and will announce it to those interested on the mailing list. All other parts are in house already, manuals printed, packaging ready and beta tests successfully completed. Our living rooms look like a warehouse now.

    Of course the kit will ship with some demo applications built-in. My focus is for a part still on those, but equally important is that the programming core is stable and tested. For me it is crucial that the memory map is well-defined and the 16-bit interpreter is fully tested and useful. After all, the vCPU opcodes are jump offsets, so it will be impossible to fix any of that later while maintaining compatibility as well. Last week I found I had some unused space in the interpreter code page, so I added some new bit-wise logic instructions and support stack variables. Surprisingly, none of the applications I wrote so far needed those.

    To test, I ported my old n-Queens solver. It exercises bitwise logic and recursion, so it is a good test for these new instructions. On the screenshot above you can see it gets the correct answers for the sequence.  The solver uses 5 stack variables. That, plus one for the the return address, gives 12 bytes per invocation. With the stack living in the top half of the zero page, this means we can go 10 levels deep. The solver needs less than a minute to compute the list, or at about 850 recursions per second. [Edit: I just figured that it should be easy to go down to using 4 variables or 10 bytes, and with that up to 12 levels deep.]

    Although 8-bit assembly programs must be programmed in the EPROM, interpreted programs run from RAM. The built-in applications are of course stored in ROM also, but they are loaded into RAM first, so they use the ROM merely as a disk. Interpreted programs can also be loaded into RAM directly over the input port, and this is how you can program the Gigatron without using an EPROM eraser and programmer. For this I hook up the input port pins, that normally go to the game controller, to a simple Arduino. The Arduino can send data at the same rate as the horizontal sync. With some checksumming overhead, this boils down to exactly 28k8 payload bits per second. Much faster than loading C64 programs from tape back in the day... (3000 baud with speed loaders!)

    The loader was the last part of the software that needed debugging with a scope.

  • Mandelbrot from TTL

    Marcel van Kervinck01/22/2018 at 00:33 7 comments

    I got a bit stuck with the work I was planning for today, so I wrote something else to regain motivation: a fractal! Rendering takes a while (8242 seconds), being fully interpreted and lacking multiplication, and even without the "right-shift" operation you badly need for this. All those must be mimicked with slow high-level code using just addition and subtraction. [Edit: it takes 1127 seconds now with native code for "right-shift"]

    It should be easy to speed the whole thing up a lot just by adding a right-shift assembly function. Next time... GCL source code:

    {-----------------------------------------------------------------------+
    |                                                                       |
    |       Mandelbrot fractal                                              |
    |                                                                       |
    +-----------------------------------------------------------------------}
    
    gcl0x
    
    {
      Plot the Mandelbrot set
    
      - 160x120 pixels and 64 colors
      - Faithful translation of mandelbrot.c pre-study
      - Use 16-bit vCPU math as 7-bit fixed point arithmetic (1.00 -> 128)
      - Implement multiplication in interpreter
      - Implement shift-right in interpreter as well
      - A bit slow (8242.655 seconds)
    
      XXX At the end change all to grey tones and redo
      XXX Redo at different sections
      XXX Tone for every pixel value
    }
    
    {-----------------------------------------------------------------------+
    |                       RAM page 3                                      |
    +-----------------------------------------------------------------------}
    $0300:
    
    { Pretty accurate multiply-shift ((A*B)>>7), but it can be off by one }
    [def
      push
    
      {Extract sign and absolute values}
      0 sign= C=
     {0}A- [if>0 A= 1 sign=]
      0 B- [if>0 B= sign 1^ sign=]
    
      {Multiply}
      7 shift= {Pending shift}
      $200
      [do
        bit=
        -$4000 C+ [if<0
          C C+ C=
        else
          {Shift prematurely in an attempt to avoid overflow}
          B ShiftRight! B=
          shift 1- shift=]
    
        {Add partial product}
        A bit- [if>=0
          A=
          C B+ C=]
    
        bit ShiftRight! if<>0loop]
    
      {Shift}
      [do
        C ShiftRight! C=
        shift 1- shift= if>0loop]
    
      {Apply sign to return value}
      sign [if<>0 0 C- else C]
    
      pop ret
    ] MulShift7=
    
    { Calculate color for (X0,Y0) }
    [def
      push
      0 X= XX= Y= YY= i=
      [do
        i 1+ i= 64^ if<>0           {Break after 64 iterations}
    
                                    {Mandelbrot function: z' := z^2 + c}
        X A= Y Y+ B= MulShift7! Y0+ Y= {Y = 2*X*Y + Y0}
        XX YY- X0+                  X= {X = X^2 - Y^2 + X0}
    
                                    {Calculate squares}
       {X}A= B= MulShift7!          XX=
        Y A= B= MulShift7!          YY=
    
        -$200 XX+ YY+ if<0loop]     {Also break when X^2 + Y^2 >= 4}
      i
      pop ret
    ] CalcPixel=
    
    {-----------------------------------------------------------------------+
    |}\vLR>++ ret{          RAM page 4                                      |
    +-----------------------------------------------------------------------}
    $0400:
    
    [def
      push
    
      $7ff p= {Start of video (minus 1 to compensate for 1st step)}
    
      -323 X0= 3 DX= 161 Width=  {Horizontal parameters}
      -180 Y0= 0 DY= 120 Height= {Vertical parameters}
    
      [do
        {Length of next segment, either horizontal or vertical}
        DX [if<>0 Width 1- Width= else Height 1- Height=] if>0
        [do
          len=
    
          {Step in the fractal plane}
          X0 DX+ X0=
          Y0 DY+ Y0=
    
          {Matching step in video frame}
          DX [if<0 p 1-     p=]
          DX [if>0 p 1+     p=]
          DY [if<0 -$100 p+ p=]
          DY [if>0  $100 p+ p=]
    
          63 p. {White while busy here}
    
          {First check if we are inside one of the main bulbs for
           a quick bailout (Wikipedia)
           (x+1)^ + y^2 < 1/16}
          Y0 A= B= MulShift7! YY=
          X0 128+ A= B= MulShift7! YY+ 8- [if<0 0
          else
    
          {q*(q + x - 1/4) < 1/4*y^2, where q = (x - 1/4)^2 + y^2}
          X0 32- A= B= MulShift7! YY+ {q}
          A= X0+ 32- B= MulShift7! tmp=
          tmp+ tmp= tmp+ tmp= {*4} YY- [if<0 0
          else
    
          {Otherwise run the escape algorithm}
          CalcPixel!
          ]]
          p. {Plot pixel}
          len 1- if>0loop]
    
        DY tmp= DX DY= 0 tmp- DX= {Turn right}
        loop]
      pop ret
    ] CalcSet=
    
    {-----------------------------------------------------------------------+
    |}\vLR>++ ret{          RAM page 5                                      |
    +-----------------------------------------------------------------------}
    $0500:
    
    { Stupid shift-right function }
    { XXX Better make a SYS extension for this }
    [def
      a= 0 b=
      $8000 a+ [if>=0 a= $4000 b+ b=]
      $c000 a+ [if>=0 a= $2000 b+ b=]
      $e000 a+ [if>=0 a= $1000 b+ b=]
      $f000 a+ [if>=0 a= $0800 b+ b=]
      $f800 a+ [if>=0 a= $0400 b+ b=]
     $fc00 a+...
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  • Hacker spaced

    Marcel van Kervinck01/19/2018 at 23:54 0 comments

    While waiting for the last parts to come in for the kit version (waiting can be so tedious), Walter and I had the privilege to be invited at two nice hacker spaces last month where we could talk about the project. So besides 34c3, we also visited RevSpace and Hack42 in the previous weeks. What a blast and what a great diversion from endlessly plowing through the kit details! Each time we met with plenty of great people with cool projects and had the chance the pick up many new ideas an suggestions.

    The first talk at Hack42 was recorded and is on youtube. It is a bit over an hour where Walter talks through the entire design including Q&A. Enjoy!

  • 930 logic gates

    Marcel van Kervinck12/30/2017 at 23:41 0 comments

    While playing Gigatron Snake at 34C3 we got asked: "how many gates are in there?". This isn't the first time someone has asked, so today I finally went through the TTL datasheets and counted little blocks from their logic diagrams. TL;DR: the CPU has 930 logic gates.

    And because 34C3 is such an inspiring place, after one day of hacking those gates now happily animate this beginning of a Racer game:

    Gate counting isn't as straightforward as it seems though. RAM and ROM are clear: they each have thousands of logic gates in their word line decoders alone, but those aren't part of the CPU proper. The clock isn't part of the CPU either, but that's just a couple of inverters. For decoding the game controller it isn't as clear cut: the kit version has a 74HC595 shift register which has roughly 80 gates. But only 10 buffer gates are really needed by the CPU and are directly controlled by it. I fact, on the breadboard version, the input chip is just a 10-gate 74LS244 non-inverting buffer. So I count that as one 10 for the CPU. I also didn't count the "extended output" register as part of the CPU because that is an extension on top of its primary output.

    I did include all other gates that are in the IC packages: An unused module is in the count (there is one unused decoder in the control unit), as well as gates that are hooked to fixed inputs (L or H), even though all of those can be optimised away in VHDL. The 4-bit adders each have 4 non-inverting buffers internally that have no logic function, but I still include them. Furthermore, I count D-type flipflops as 5 gates, and SR-types as 4. Still, the total gate count of 930 is a lot lower than I would have guessed.

  • Tail chasing its head

    Marcel van Kervinck12/23/2017 at 12:36 0 comments

    To make 64 colors, every pixel occupies 6 bits of a byte in RAM. The two high bits can have arbitrary values as they are masked by the pixel burst loop. This opens up all kinds of tricks. For example, they can encode play field information for a game: where there are walls, independent of their color. Here I use these bits in the snake segments: they keep track of direction so the tail can follow the head. Like invisible breadcrumbs. Up/down/right/left just needs 2 bits... 

  • SYS calls for accelerating interpreted programs

    Marcel van Kervinck12/18/2017 at 13:04 0 comments

    The virtual CPU or interpreter is now complete. At least, its code page is full, even overflowing a bit, and nothing can be added without removing something else. It has 25 opcodes, the last added is SYS. This is an escape: with SYS the application can jump to arbitrary native code. Here I test this capability in the "clear screen" loop, right at the beginning of the recording.

    Without acceleration, clearing the screen pixel by pixel with interpreted code takes more than 2 seconds. Here the application uses a SYS call that clears 8 pixels at a time. The result is that the screen now clears in 200 ms. Nice proof of concept.

    Restrictions apply if you don't want to break the video timing: the callee must be timing-aware and cooperate with the interpreter loop. But it can run for longer than a regular vCPU instruction (these are 28 cycles max) and the code can do whatever it wants, as long as it completes in the available time slice on the scan line. In reality this means that SYS calls can last for up to 146 cycles. If they need more cycles, they could still use some trickery and restart themselves by messing with the virtual program counter... They are "parasitic" after all.

    Another novelty is that this recording is not from an actual Gigatron! Martin @ the talkchess forum has made an incredible visualisizer for the project. I didn't get it running with the Mac binary, but it runs ok with Wine. Emulation in emulation in emulation, but it can still keep up with real time if you use "Run sketch (JIT)". Amazing.

    There is some latency with the sound, but that is fine. This tool already saved me a tons of EPROM burning cycles. For the real experience, just use a real Gigatron...

    P.S: The Christmas card is there to give my phone something to focus on. Without it the recording is blurry.

  • Gigatron! The TTL computer as a kit

    Marcel van Kervinck12/06/2017 at 21:03 1 comment

    Some months ago my good friend Walter has silently joined the project. The reason is that I receive a lot of enthusiasm whenever I show this to friends, to the point where one is already seriously trying to write a chess program for it. So we decided to take this one step further and upgrade this to a build-it-yourself soldering kit. Today we received the first samples for the enclosure, custom designed for this computer.

    With a new phase comes a new name. Neither of us really liked the "Chipper" working title I used before, so the kit version will be known as the "Gigatron TTL microcomputer".  I couldn't possibly do this all by myself, so I'm super happy that Walter has stepped in. 

    This retro-computer is something to build, play with but also look at, so we plan to offer it as complete as possible, except for the soldering you will have to do yourself. So it will include all the 74xx-TTL chips, RAM, ROM, sockets, capacitors, diodes, resistors, LEDs, supervisory circuit, jacks, a game controller, a nice mahogany coloured wooden enclosure with plexiglass viewing window, one or two built-in video games and a mini-USB cable for power. Not all details are finalised yet: the photo is a prototype and we will still change some things we don't like. We think we can target the 150-180 euro price range (hopefully below 200 dollars), provided there is sufficient interest. For reference, getting to the first PCB version set me back north of 500 euros, that is where I stopped counting, and that excludes the oscilloscope you need when designing something like this from scratch. And did I mention the 800 hours of research, trial and error? This is still just a private hobby project, so this kit will be something we will literally do from our living rooms. We figure that if we do a few dozen units that would push the prices down a lot and at the same time not take too much risk.

    Of course a kit isn't the same as a one-off project, and Walter has worked tirelessly on morphing the project towards something that can be reliably soldered together in 3 to 4 hours. All components are now through-hole components and sourced from proper sources (not scavenged from e-bay). Walter has written a supercool manual that includes intermediate tests, a circuit diagram and even soldering instructions and tips for novices. Although there are 144 components on the board (many capacitors and diodes), I feel it will still be a beginner's level kit because of the spacing and all through-hole components. All you need is a soldering iron, solder, a multimeter, some pliers and a rainy Sunday afternoon. If you can make Oscar's PiDP-8, then you can make this also.

    For those interested in this kit, you can subscribe to our mailing list. We will use this mailinglist only to announce when we are comfortable to accept orders, know the exact pricing and have some kits ready to ship. Subscribing to the mailing list doesn't imply any obligation to buy: it is just a way to keep informed of when we are ready and you can easily delist as well. We expect we will be ready near the end of January. It will then also be clear what the final kit looks like, what the built-in software can do, etc.

  • 16-bit subtraction and ROM tables

    Marcel van Kervinck12/05/2017 at 20:37 0 comments

    Two small steps in software land: With 16-bit subtract we can bounce a ball properly. With ROM tables we can finally render the 5x8 font I designed some time ago. (In the video below I forgot to add letter spacing, so the characters are all smashed together.)

    16-bit subtraction turned out to be a bit harder than I hoped for. The difficulty is that without a status register you must somehow reconstruct the carry in software. This boils down to ugly bit fiddling with nasty edge cases, and is frustrating, knowing that the minimalistic hardware has just thrown the same carry away. But it can be done and needs to be solved just once. The interpreter can now do it at the same speed as 16-bit addition: 28 cycles including interpreter overhead.

    For the more time-critical sound oscillators, they run in every horizontal blank, I use a much faster 15-bit scheme (7+8), reserving 1 bit in the lower byte for carry. That works, but for the application interpreter I want proper math.

    We now also have ROM tables accessible from within the interpreter. This means that it becomes easier to stuff lots of data and programs in ROM, and load any of it into RAM whenever needed and without disturbing the video loop.

    Two nice steps towards a useful application environment.

  • Game compiler

    Marcel van Kervinck11/30/2017 at 20:50 2 comments

    The inner interpreter decouples the harsh video timing from the application code. It runs whenever the video/audio/input handling has nothing to do, typically during vertical blank, and in every 4th scanline of the visible video. It reads instructions from RAM and dispatches to their native implementation. It works very much like SWEET16 on the Apple II, except that it also tracks their duration: when there is not enough time left for another instruction, it re-syncs with the video timing and returns control. To make programming easier, I wrote a simple offline compiler that provides a compact text notation with block structure, "if", "loop" etc.. Here is the beginning a game made in this:

  • Moving up the ladder of abstraction

    Marcel van Kervinck11/12/2017 at 17:54 0 comments

    This photo captures the inner application interpreter's first sign of life. Very early this morning, or late last night, the virtual CPU ran its first program. It calculated the largest 16-bit Fibonacci number to be 1011010100100000 and plotted that in the middle of the screen. The video loop was still playing the balls and bricks game, unaware of what was happening, but sometimes the ball bounces off the 16-bit result.

    The interpreter is the virtual CPU that makes it possible for mere mortals to write applications without worrying about the arcane video timing requirements.

    For this test I hand-compiled the BASIC program into interpreter code and preloaded it into RAM. Shown here is the interpreter running during every 4th visible VGA scan line. It dispatches instructions and keeps track of their duration until it runs out of time for the next sync pulse. It can't stream pixels at the same time so these lines render black. I don't mind the bonus retro look at all.

    With this the system undergoes quite a metamorphosis:

    • The TTL computer: 8-bits, planar RAM address space, RISC, Harvard architecture, ROM programmable
    • The inner virtual CPU: 16-bits, (mostly) linear address space, CISC, Von Neumann architecture, RAM programmable

    A typical interpreter instruction takes between 14 and 28 clock cycles. The slowest is 'ADDW' or 16-bits addition. This timing includes advancing the (virtual) program counter and checking the elapsed time before the video logic must take back control. It also needs a couple of branches and operations to figure out the carry between low byte an high byte. That is the price you pay for not having a status register. But is that slow? Lets compare this with 16-bit addition on the MOS 6502, which looks like this:

    CLC     ;2 cycles
    LDA $10 ;3 cycles
    ADC $20 ;3 cycles
    STA $30 ;3 cycles
    LDA $11 ;3 cycles
    ADC $21 ;3 cycles
    STA $31 ;3 cycles
            ;total 20 cycles or 20 µsec

    The TTL computer executes its equivalent ADDW instruction in 28/6.25MHz = 4.5 µsec.

    We should be able to get out roughly 60k virtual instructions per second while the screen is active, or 300k per second with the screen off. So I believe the interpreter's raw speed is quite on par with the microprocessors of the day. The system itself of course loses effective speed because its hardware multiplexes the function of multiple components: CPU, video chip and audio chip are all handled by the same parts. And to make things worse, the computer "wastes" most of its time redrawing every pixel row 3 times and maintaining a modern 60Hz frame rate. PAL or NTSC signals of the day were 4 times less demanding than even the easiest VGA mode.

    Next step at the software front is finding a good notation for the source language.

    On the hardware side, there is some progress on a nice enclosure. I hope to have a preview soon.

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Marcel van Kervinck wrote 12/26/2017 at 07:12 point

Anyone attending 34C3 in Leipzig this week: we will be strolling around, and of course we'll bring Gigatron prototypes!

  Are you sure? yes | no

monsonite wrote 11/08/2017 at 18:28 point

Hi Marcel,

Great work!  Faster, simpler and cheaper than the original IBM PC - love it!

Is there a schematic available for your design?  I'm interested in the final approach you took for your ALU.

Interested to hear some more about the virtual machine you hinted upon.

I have shared your work with anycpu.org

Well Done

Ken

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Marcel van Kervinck wrote 11/08/2017 at 19:10 point

The full schematic might appear in some later stage as it is quite a mess in need of serious cleanup and I'm working on software the upcoming weeks. But the ALU is described adequately elsewhere: the "Logic" stage comes from here  http://www.6502.org/users/dieter/a1/a1_4.htm  (bottom of the page) and the ALU uses two of those with two 4-bit adders, as described here: http://www.6502.org/users/dieter/a1/a1_6.htm  except that my design does without the 3rd stage that only provides right-shifting. So in total it is 8x'153 and 2x'283 with 5 control signals going in. Dieter's pages suggest that you need 8 signals, but most of them have the same value for the common operations. The carry-out goes back into the condition decoder where it acts as an allzero-indicator during jumps. There is no flags register as it costs too many chips for too little added value. I do right-shifting in software using the "single-instruction subroutine" technique described in the log on pipelining. This computer doesn't need shifting that much because the graphics layout is 1 byte = 1 pixel.

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monsonite wrote 11/11/2017 at 18:33 point

Hi Marcel,

I'm suitably impressed with the elegance of your design that I have taken time to transcribe it to EagleCAD, so that I can get a better understanding of the control and data paths.

After pondering your Control Unit schematic for an hour yesterday lunchtime, and how it decodes the ALU instructions and generates the various addressing modes and jumps, I was happy that I could figure from the bus and dataflow diagram how most of the rest of it worked. 

Now that the bulk of the design is captured, I'm figuring out a way of using an ATmega1284 as an easy to update ROMulator device, running code from faster RAM and a way of extending by adding more VRAM.

When you consider that the first Sinclair ZX80 machine took 18 TTL chips, plus Z80, ROM and RAM to create a monochrome TV picture of 32 x 24 8x8 characters, for just another 18 chips they could have replaced the Z80 and had something that produced colour graphics and ran at 4 or 5 times the speed.

regards

Ken

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Justin Davis wrote 01/02/2018 at 16:51 point

I don't think schematics are ever really "finished", but the schematic that the layout was made from would be most helpful even if it is a mess.  I would like to see them because I would like to try to recreate it in an FPGA.  You could post them now, and then replacement them with a cleaned up version once you have it finished.

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Yann Guidon / YGDES wrote 10/28/2017 at 12:41 point

Amazinger :-D

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f4hdk wrote 05/26/2017 at 11:34 point

I like it! 

Every homebrew computer should have video output, even made with TTL!

Have you seen my project? It is quite similar (custom CPU architecture, video output) even if I used an FPGA  instead of TTL components.

https://hackaday.io/project/18206-a2z-computer

It's fully documented and open source. 

And welcome on the "homebrew CPU Webring" !

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Marcel van Kervinck wrote 05/26/2017 at 13:52 point

Nice! FPGA's are a step up for me. Clearly the TTL and the RAM size are limiting my video resolution, but it is also cute in its own way.

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Peabody1929 wrote 04/01/2017 at 18:46 point

Consider one or two AMD2901 or a single CY7C115/116/117 -> More computer, fewer chips.

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Marcel van Kervinck wrote 04/02/2017 at 20:09 point

Thanks. I can find the first. I do have ALU chips available, I just don't feel like using them in this build. Do you have data sheets for the second series? I have trouble finding out what it is. Some memory? I plan on using 62256 for RAM and 2x AT28C256 for ROM, with a possibility to extend the memory using the AT27C1024.

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Big Boy Pete wrote 03/31/2017 at 18:19 point

Good luck Marcel.

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