First the instructions- Each instruction is of 16 bits that means [15:0]. Further dividing it
we select opcode- [15:12] then rest [11:0] bits depend on the instructions.
For R type we have
ADD [--R1--] [--R2--] [--R3--] Each Register here is of 4 bits.
So number at location of R1 added to number at location of R2 will be stored at address pointing to R3 register.
SUB [--R1--] [--R2--] [--R3--]
Similarly we have for subtract too.
Ex- 0001 0001 0010 0111
it means 0001 for SUB opcode 0001 is address of R1 0010 is address of R2 and 0111 is address of destination R3
Now for I format we have Load Word and Store Word
LOAD [--R1--] [--R2--] [--sign extend--]
now number stored at R1 will be added to sign extend and the result will be an address pointing to a location in RAM. the data from RAM is then stored in R2
Ex- 1011 0100 0111 1010
Sign extend of 1010 is 11111010 added to data at location 0100 and result will be stored at location 0100 in Register
STORE [--R1--] [--R2--] [--sign extend--]
ex 1100 0100 0111 1010
Sign extend of 1010 is 11111010 is added to content of 0100 and we get an address of RAM. Then the content of 0111 is stored in that address of RAM.
Branch format- I have included only one branch function.
Its BEQ (Branch if equal)
Ex 1101 0010 0100 0111 if the contents of 0010 and 0100 are same then Z flag wil be triggered and with that PC wil increment by 1 which will be added to 0111 a.k.a 3 in decimal. This will be the amount of instructions by which PC will jump.
Jump fprmat- Currently this peocessor has only one Jump instruction
its JMP (unconditional)
Ex 1110 000000001010 The next PC (PC + 1) [15:0] will apart a wire with PCout[15:12] and will concat with the above 12 bits (00000001010) and will jump to directly to the instruction pointing to above address
Open Xilinx and Create a new project. Then add source (Verilog) and paste ALU code.
Make similar modules for each. Then create a module which connects all those modules which is datapath. If done correctly all remaining modules will mo.e under a hierarchy of datapath module. The control Unit will remain in another module and not in datapath. (Not necessary but for atleast my design). The risc top module will include both control module and datapath module.
Now Right click and add source and this time select Verilog Test Fixture and not module.
Then remove #100 and paste "#30 $finish" to finish simulation after 30ns.
Then in initial begin clk=0 and reset=0.
"After the initial block" type this " always #1 clk = ! clk; " (without quotes). This is the clock generator.
At top left you must select simulation. Then select topmost module i.e fixture and click "Simulate Behavioral Model" Then a new window opens.
Click on left triangle shaped arrow and there you can select all signals you want so see.
Then click on RE-Launch at right top and Voila !!