Basically a shift register is a sequence of outputs triggered one at a time by a clock signal.

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Just for fun I designed a logic gates network for a 4 bit shift register.

Once the network is supplied the first stage turns on and keeps that condition until the clock pulse is sent.

As you can see in the logic diagram, the gate number 1 turns on if the clock input and the previous stage are both activated. But the gate number 2 gets high if the previous stage is first activated: this prevents the clock signal from triggering all bits at the same time.

Each of the stages number 1-2-3 are disabled through the gate number 8.

This shift register has been tested with an online logic gate simulator.