LLTP - Light Logic Transistorless Processor

My attempt to create a CPU/MCU without transistors or relays

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A processor using only handmade opto-couplers? I am a bit behind in working with this idea but I want to recreate my IO Cardboard Computer without the use of any transistors. This project will make full use of my Light Logic gates. See also AND

My interest in logic gates that did not make use of transistors started about two years ago. After about six months of hair pulling, yelling and cursing I was able to create the entire Boolean logic set using just diodes and resistors. Granted the key diode is a LED and the key resistor is a CdS Photo Resistor. Granted I do not expect anyone to think that this processor build will be fast or practical but is part of a grand "What If" idea I had and Light Logic was born. Now it is time to put those logic gates to work and see if a working processor can be constructed this way. So as to not confuse my senior moment prone brain, I will keep the logic gates down to just NAND and NOT except for the diode only AND gates used in the 4 to 16 line decoder on the Hex display module. The other Light Logic gates I have made will work but do not always play nice with each other and inverting logic just seems to work better for me.

  • 1 × White Led
  • 1 × LDR CdS Photo resistor
  • 2 × 1N914 switching diode
  • 1 × Resistor 330 Ohms Use this value for a 3 Volt supply
  • 1 × Parts listed above are for each 2 input Nand gate

  • State Machine Size Reduction

    Dr. Cockroach12/11/2022 at 16:07 0 comments

    December 11, 2022 - Yup, sounds like a weight reduction goal and this is the first phase. My wall sized panels were.......Well....... wall sized and taking up too much space. This first step is wiring the State Machine onto some perf board and once that is de-bugged I will do the same for the ALU. The following is the major parts layout for the SM.

  • A Refind Adder with Xnor Gates

    Dr. Cockroach06/18/2022 at 10:42 0 comments

    June 18, 2022 - I have spent way too much time away from my Light Logic projects but recently had the idea to take the current LLTP build and re-think the logic gates I have been using and try to reduce the number of gates used. The Full Adder seems to be the first area to work on and I have started on testing a Adder on Logisim that instead of using only Nand gates I will make use of a pair of Xnor gates and a 2 X 1 Mux. This will reduce the Light Logic gate count from nine to six gates for a single bit Full Adder. Over the course of a four or eight bit adder this will save me quite a few gates. Each gate requires a single opto coupler/vactrol an a few support diodes.

    Logisim likes the circuit so far, so next will be a actual build and test.

  • Final end of 2021 Circuits for Light Logic Gates

    Dr. Cockroach12/31/2021 at 23:52 0 comments

    December 31, 2021

    Not earth shattering but here are the final circuits for Light Logic. Happy New Year to everyone.

  • A little improvement on the XNOR gate

    Dr. Cockroach12/28/2021 at 14:14 1 comment

    December 28, 2021 - After a bit of an absence I started improving on some of my Light Logic gate circuits. I was never satisfied with how my XNOR gate turned out so I ended up having a dream last night and when I woke up this morning I got to working on what I had dreamed about. The simple change is that I now feed 5 volts to the inputs continuously through a pair of 150R resistors. If there is no input at either A or B then the input is considered HIGH. If either A or B is grounded through a previous gate then the input is LOW. The Out of the LDR can be followed by a Light Logic Inverter gate to create a XOR gate or wired to any other gate as needed. I have this circuit on a bread board and it is working as it should. Remember, with Light Logic  the output MUST be through the LDR to ground to be a counted as a solid Zero / Low. Anything else is counted as a One / High

  • As small as it gets for now

    Dr. Cockroach11/01/2021 at 21:52 7 comments

    November 1, 2021 - Finally finished up the newest D-Latch with a added output buffer. This build works just as well as the wall mounted LLTP D-Latches and is about as small as I can make with my standard way of hand making my Vactrols. The solder side is not pretty but the same layout as if it were a PCB.

    Just to recap, the added output buffer is needed as the Q output can be de-latched when fed directly to the next stage such as a adder or another part of the processor.

  • A new smaller look

    Dr. Cockroach10/25/2021 at 16:54 0 comments

    October 25, 2021 -  I have been idle on the LLTP for a little longer than I wanted but I have been doing a bit of mind games on where to go with the construction of this 4 bit no transistor processor. I am trying out my standard Light Logic Vactrol devices on a copper perf board and making the parts placement as tight as I can.  The follow images look promising and show the partial wiring of a one bit latching memory. So instead of a design that will take up the walls of my lab, the new reduced design will only take up a table or desk top or mounted on something like a motherboard.

  • August 19, 2021 - Just Hanging Around....

    Dr. Cockroach08/19/2021 at 12:22 0 comments

    Finally getting the LLTP hung onto the lab wall like I wanted from the start of this project.

  • All Led NAND Gate

    Dr. Cockroach04/06/2021 at 10:33 0 comments

    April 6, 2021 - just for grins and future use. A Light Logic 4 input NAND gate where all the diodes are Leds and in free form without the paper and fasteners.

  • LLTP has a display

    Dr. Cockroach03/20/2021 at 23:06 2 comments

    March 20, 2021 - I'm back and melting solder once again. I adapted the hex display used on the Cardboard Computer - IO project and replaced the transistors with Light Logic. The display is not perfect by a long shot but it does work.

  • Comming back to life

    Dr. Cockroach01/21/2021 at 01:25 5 comments

    January 20, 2021 -  Well now, where to begin. My last entry was on December 5th and the very next day I started feeling a bit odd. My sense of smell and taste vanished in a matter of days and just felt weak. By Dec 10th I had lost 10 pounds of fluids and I felt that I had to go to the ER. Many tests and scans done and YUP, Covid-19. I was put on IV and felt a little better after that but for the next 4 days I was running a fever that would not break. I was having a hard time breathing by this point so off to the ER again. CT scan did not show any lung issues to be worried about but was given another IV, That's now two liters plus a steroid of some sort. Given a script and went home. The fever broke about four days later and I have been making slow progress. Now by Jan 20 I have my energy back in full though still have a bad cough from time to time. This has been a roller coaster ride that I would not wish on anyone. My appetite has also changed as I feel hungry but can only manage about half of what I used to eat. After my fluids were back to normal and my weight briefly returned to 254 pounds. My reduction in eating has me down to 239 as of this morning. I look forward to losing some weight but by way of the CV is not advised.

    I will get back to this project as I have sat on my arse for too long :-)

View all 24 project logs

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Peabody1929 wrote 12/12/2022 at 02:23 point

You can reduce size by reducing the number of gates required.  Any function can be implemented by two layers of gates.  The first layer is AND (NAND), while the second layer is OR (NOR).  PAL devices (ex 22V10)  use this approach. To optimize the number of gates, Karnaugh maps can be used.  Check out this URL: 

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Dr. Cockroach wrote 12/24/2022 at 15:35 point

Very true. I am still a babe in the woods, logic wise, so a lot of learning by doing.

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Boxerbomb wrote 08/09/2023 at 19:41 point

That is actually not correct, although it is sometimes incorrectly taught that way in schools. Sum of Products form reduces the propagation delay of circuits(depending on available gates), but not the number of gates or transistors. Minimizing logic is actually an unsolved problem and there are still advances made every year. For example, a full-adder using the SoP approach uses 9 gates if each gate can have an arbitrary number of inputs, or 16 gates if limited to 2-inputs per gate. On the other hand, a full-adder using 2-input XORs, 2-input ANDs and 2-input ORs, only uses 5 gates.

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Dr. Cockroach wrote 08/10/2023 at 11:07 point

Thanks Boxerbomb, propagation delay is not a concern as the reaction delay of the LDR is already in the many milliseconds so not looking to make a speed demon cpu ;-) I do now have a working XOR and XNOR using just a single gate or two and I am also working on another project that replicates a 74181 ALU , gate for gate using my Light Logic . These projects are in slow mode but learning a lot from them :-)

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Ken KD5ZXG wrote 08/10/2023 at 21:22 point

Full adder in two LLTP majority gates already proven, though some cases need more gain to fully clip a clear answer. Differential majority flipflops with positive feedback might work, but four LDR for two gates. Still less than five... 

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aldolo wrote 10/25/2021 at 18:00 point

wow. it's a pity the light must stay within the black case

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Dr. Cockroach wrote 10/26/2021 at 13:31 point

Yest it is but the blackout is needed to shield the photo resistor from stray light. The base lets out a little light so in a dark room you can view the changes in logic levels. I am learning a lot with this long term build :-)

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DaveBoltman wrote 09/17/2020 at 07:05 point

Wow! I logged in here to point out that optocouplers contain transistors, but your's don't!

Fascinating to watch. Well done so far, and all the best!

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Dr. Cockroach wrote 09/17/2020 at 09:49 point

Thanks, Doing without transistors was an itch that I just had to scratch and a lot more to come :-)

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Dr. Cockroach wrote 08/15/2020 at 00:26 point


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Dr. Cockroach wrote 08/16/2020 at 14:00 point

Actually two of the thirty ;-)

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Dr. Cockroach wrote 08/06/2020 at 11:38 point

@Tim Even stranger in my case as this project does not use any transistors. The logic being performed by a Led/CdS photo resistor pair. Nands all the way now and all is working as should. And yes, I tried to condition the levels but then as you said I ended up with just as many gates as if just going the Nand route :-)

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Yann Guidon / YGDES wrote 07/29/2020 at 18:46 point

Daaaaamn... Do you remember you can make a XOR easily with your system without having to use NANDs ? :-D

Put a diode in series with a LED between 2 signals and you have the gate ANDN (A='1' and B='0'). Then you put the LDR in parallel so you get A&/B + /A&B !

And you can make it even simpler when you do it at the LED side.

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Yann Guidon / YGDES wrote 07/29/2020 at 18:47 point

Oh my I didn't read all the logs ;-)

Sorry dude ;-)

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Yann Guidon / YGDES wrote 07/29/2020 at 18:54 point

So what is the problem with the XOR cells ?

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Dr. Cockroach wrote 07/29/2020 at 20:39 point

Thats OK, The LL XOR works great as a stand alone gate but when followed by another XOR as in a adder circuit, the voltage out for a one and a ground for a zero goes kind of wonky and is not reliable as it now stands. It was then that I decided to just make the entire build out of Nand gates knowing that they link well one to another :-) Never fear, I'll return to the LL XOR later and work on it :-)

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Tim wrote 08/06/2020 at 03:25 point

>the voltage out for a one and a ground for a zero goes kind of wonky and is not reliable as it now stands

Sounds very familiar from all the weird XOR tricks. One cannot use these gates without a level restorer and then the advantage in reduces component count or tpd is already gone.

(Had to patch some inverters into my last project exactly due to this... Spice does not help if you don't have proper spice models of the chinese off-brand transistors you use...)

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Ken KD5ZXG wrote 12/06/2020 at 21:29 point

NXOR may be a little easier than XOR. NXOR into NXOR also yields SUM. Give each input a Schottky to pull-down, and resistor pull up. Then a Schottky bridge between them to feed one LED.

SUM isn't difficult. The challenge is a fast ripple Carry. MAJ3 in a single gate rather than four NANDs gives different light and LDR resistance for majority 2/3 carry than it does for unanimous 3/3 carry. If MAJ3 output fans twice (by double weighted pull-up) into MAJ5 to compute SUM, and another MAJ3 for ripple, inconsistent analog levels here do not mix well. Carry=MAJ3(A,B,C). SUM=MAJ5(A,B,C,/Carry,/Carry)

No simple way to drop my unbuffered breadboard photo into comments. But this two gate LDR adder does actually work, just barely. Really wants an extra pair of inverters to better clean up the results. Together with inverters, should still be far fewer parts than NAND.

Unbuffered MAJ driving NAND isn't a problem. Unbuffered MAJ driving MAJ is, as well some XOR schemes. There is just not enough gain here to assure full output levels and reasonable fanout for every style of whacky gate one might dream up. And I've tried some whacky ones...

Also had no luck using light manifolds to OR multiple LEDs onto a single LDR. Each LDR wants LED on dead center, else the gain is unacceptably low. And many LDR in wire OR (one LDR per LED) more easily accumulate unacceptable leakage. 

My other thought might be LCD shutter glass. As the light source could be arbitrarily bright and always on. Large LED current need not flow through LDR ON resistance, which can easily be over 100R. But would a shutter or stack of them be dark enough and transparent enough for an LDR to make good levels to drive a fanout of other shutters?

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Starhawk wrote 06/13/2020 at 22:37 point

Go for it, dude -- Godspeed :D

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Dr. Cockroach wrote 06/13/2020 at 22:39 point


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