x-dia-diagram - 7.42 kB - 09/29/2019 at 05:07

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x-dia-diagram - 4.74 kB - 09/29/2019 at 05:07

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YGREC8_VHDL.20190422.3.tgz

R7 decoder in A3P tiles

x-compressed-tar - 174.65 kB - 04/22/2019 at 01:39

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YGREC8_VHDL.20190422.tgz

a better decoder for the register set

x-compressed-tar - 173.01 kB - 04/21/2019 at 17:58

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YGREC8_VHDL.20190421.tgz

Redesigning the register set

x-compressed-tar - 155.92 kB - 04/21/2019 at 00:13

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YGREC8_VHDL.20190412.tgz

New gates library, better ALU and decoder

x-compressed-tar - 152.59 kB - 04/11/2019 at 23:23

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YGREC8_VHDL.20190404.tgz

more versions of the ALU8 decoder

x-compressed-tar - 148.85 kB - 04/04/2019 at 23:10

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YGREC8_VHDL.20190401.tgz

spun off the decoder logic for deglitching

x-compressed-tar - 144.44 kB - 04/01/2019 at 02:57

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YGREC8_VHDL.20190328.tgz

ALU implemented as 3-input logic gates

x-compressed-tar - 143.44 kB - 03/28/2019 at 20:20

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YGREC8_VHDL.20190325.tgz

ALU redesigned

x-compressed-tar - 109.39 kB - 03/25/2019 at 05:22

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YGREC8_OpcodeMap_v2.svg

AND and XOR swapped for the new ALU design

svg+xml - 24.80 kB - 03/23/2019 at 01:09

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YGREC8_VHDL.20190317.tgz

new assembler/disassembler in VHDL

x-compressed-tar - 101.43 kB - 03/17/2019 at 02:53

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svg+xml - 11.40 kB - 01/13/2019 at 23:30

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svg+xml - 24.80 kB - 01/13/2019 at 22:24

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YGREC8_VHDL.20190101.tgz

assembly passes self-tests

x-compressed-tar - 114.55 kB - 01/01/2019 at 15:25

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YGREC8_VHDL.20181230.tgz

assembler reboot, not finished but promising !

x-compressed-tar - 113.57 kB - 12/30/2018 at 07:05

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YGREC8_VHDL.20181101.zip

Added the proasic3 VHDL library for rough gate-level simulations, many incoherent or obsolete files though.

Zip Archive - 109.48 kB - 11/01/2018 at 16:04

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YGREC8_InstructionFormat_v5.svg

V5 with Imm4 field

svg+xml - 10.89 kB - 11/01/2018 at 15:59

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YGREC8_VHDL.20181017.tgz

Added the ProASIC3 "tiles" library

x-compressed-tar - 60.71 kB - 10/17/2018 at 04:14

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ygrec8_20180116_yg.svg

Core diagram in SVG, added LDCx MUXes

svg+xml - 17.96 kB - 01/17/2018 at 17:38

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svg+xml - 6.99 kB - 01/12/2018 at 18:57

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YGREC8_VHDL.20171209.tgz

Added: license, readme, mustfail...

x-compressed-tar - 36.61 kB - 12/08/2017 at 23:21

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ygrec8.nanorc

Coloration syntaxique pour l'éditeur de texte Nano

nanorc - 1.16 kB - 12/08/2017 at 14:43

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ygrec_debug.svg

How the YGREC8 is split and controlled for debug, development and test

svg+xml - 8.55 kB - 12/03/2017 at 16:26

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ygrec8_20171122_yg.svg

core diagram in SVG

svg+xml - 16.46 kB - 12/03/2017 at 16:26

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YGREC8_InstructionFormat_v2.svg

Instruction format diagram in SVG

svg+xml - 7.50 kB - 12/03/2017 at 16:16

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YGREC8_VHDL.20171117.tgz

Starting to code the assembler.

x-compressed-tar - 19.08 kB - 11/17/2017 at 09:51

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YGREC8_VHDL.20171116.tgz

Executes its first instructions, and other enahncements

x-compressed-tar - 16.41 kB - 11/16/2017 at 05:28

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YGREC8_VHDL.20171114.tgz

Added some BRAM blocks and ... a core ! (it compiles but need to be tested now)

x-compressed-tar - 14.65 kB - 11/14/2017 at 06:41

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YGREC8_VHDL.20171113.tgz

much better integration now.

x-compressed-tar - 9.38 kB - 11/13/2017 at 02:19

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YGREC8_VHDL.20171112.tgz

ALU, SHL, REG, INC8, INC16...

x-compressed-tar - 7.53 kB - 11/12/2017 at 05:22

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YGREC8_VHDL.20171111.tgz

ALU, SHL and REG units, with their testbenches and 2 versions each, targeted for A3P FPGA.

x-compressed-tar - 5.69 kB - 11/11/2017 at 14:49

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ALU8.tgz

2 versions of the ALU, one testbench and one script to run it all with GHDL.

application/x-compressed-tar - 2.33 kB - 11/10/2017 at 07:06

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