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PDPii

PDP-11 compatible motherboard in mini-ITX form factor

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Buy black (not white) microprocessor 1801VM2 (КР1801ВМ2 in Cyrillic) on eBay and follow me ;)

At present PDP-11 computer systems are mostly forgotten, but there are PDP-11 compatible Soviet microprocessors still available on eBay (never used "new old stock") as KR1801VM2 (КР1801ВМ2 in Russian) and I'm going to bring PDP-11 of some sort back - I'm designing an open source computer (licensed under CERN OHL v1.2) around that chip (VM2 was 2nd version of Soviet single chip implementation of LSI-11 system [ not a clone!!! ] which could be used to build PDP-11/03 kind of machine) with open source modules and backplane in mini-ITX form factor 170*170mm (see GitLab) that could fit into regular mini-ITX computer case (that is cheap) to make a true 16-bit modern retro computer with PS/2 keyboard (and may be mouse) and connected to [S]VGA monitor:

As you can see design is inspired by famous RC2014 ;)

UPDATE1: On April 26th this project was featured on hackaday.com :)
https://hackaday.com/2018/04/26/a-mini-itx-pdp-11/

UPDATE2: Mailing list for all nedoPC projects in English: 

https://groups.google.com/d/forum/nedopc

http://groups.google.com/group/nedopc (old link)


Mini-ITX spec with all sizes could be found here

I didn't want to use Q-bus (called "LSI-11 bus" in earlier DEC documentation) as is (in it's original edge-connector form) because it's huge and almost half of contacts are not used, so I put all meaningful signals of Q-bus in 1-row header (slightly re-arranged) and in the same row (after 1 missed pin) I added all other signals from VM2 microprocessor and also de-multiplexed and inverted address lines - there are no modern ICs that could decode multiplexed Q-bus with proper handshaking natively (except for some number of old Soviet memory chips that mostly defective) so presence of already demultiplexed and inverted address will help to connect regular memory RAM and ROM chips. So it's 62-pin header (37th pin is missing) that could fit in 6.3 inches ( or 160mm that is coincidentally a limit for Eagle v5 Standard Edition that I own since 2007 ; ) and collectively I call this interface "Bread-Board friendly Q-bus extended" or BBQ-bus+ :)

PositionName (bold if Q-bus)
Where connected
1GNDGround - pin 1 and 20 of VM2
2BDMR L/DMR - pin 12 of VM2
3BSACK L/SACK - pin 13 of VM2
4BDMGI LDaisy chained BDMGO
5
BDMGO L /DMGO - pin 14 of VM2
6BHALT L/HALT - pin 29 of VM2
7BDCOK H/DCLO - pin 26 of VM2
8BPOK H/ACLO - pin 25 of VM2
9BINIT L/INIT - pin 27 of VM2
10BEVENT L/EVNT - pin 30 of VM2
11BIRQ4 L/VIRQ - pin 28 of VM2
12BIAKI LDaisy chained BIAKO
13BIAKO L
/IAKO - pin 24 of VM2
14BDIN L/DIN - pin 22 of VM2
15BDOUT L/DOUT - pin 18 of VM2
16BRPLY L/RPLY - pin 17 of VM2
17BSYNC L/SYNC - pin 21 of VM2
18BWTBT L/WTBT - pin 19 of VM2
19BBS7 LLogical 0 if A15=A14=A13=1
20BDAL0 L/AD0 - pin 9 of VM2
21BDAL1 L/AD1 - pin 8 of VM2
22BDAL2 L/AD2 - pin 7 of VM2
23BDAL3 L/AD3 - pin 6 of VM2
24BDAL4 L/AD4 - pin 5 of VM2
25BDAL5 L/AD5 - pin 4 of VM2
26BDAL6 L/AD6 - pin 3 of VM2
27BDAL7 L/AD7 - pin 2 of VM2
28BDAL8 L/AD8 - pin 39 of VM2
29BDAL9 L/AD9 - pin 38 of VM2
30BDAL10 L/AD10 - pin 37 of VM2
31BDAL11 L/AD11 - pin 36 of VM2
32BDAL12 L/AD12 - pin 35 of VM2
33BDAL13 L/AD13 - pin 34 of VM2
34BDAL14 L/AD14 - pin 33 of VM2
35BDAL15 L/AD15 - pin 32 of VM2
36PWR5V+5V (switchable) - pin 40 of VM2
37
NOT CONNECTED (a key)
38CLCICLCI - pin 16 of VM2
39CLCOCLCO - pin 15 of VM2
40A0Latched inverted /AD0
41A1Latched inverted /AD1
42A2Latched inverted /AD2
43A3Latched inverted /AD3
44A4Latched inverted /AD4
45A5Latched inverted /AD5
46A6Latched inverted /AD6
47A7Latched inverted /AD7
48A8Latched inverted /AD8
49A9Latched inverted /AD9
50A10Latched inverted /AD10
51A11Latched inverted /AD11
52A12Latched inverted...
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nedo1820_v1_0.zip

Eagle v5.1 files for RAM 32KB (16 Kwords) module - 160x70mm

Zip Archive - 50.98 kB - 05/12/2018 at 20:21

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nedo1810_v1_0.zip

Eagle v5.1 files for ROM 64K module - 160x37mm

Zip Archive - 50.14 kB - 05/07/2018 at 05:29

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nedo1800_tmpl.zip

Eagle v5.1 files for module templates: nedo1800.sch & nedo1800.brd - 160x70mm; nedo1800s.sch & nedo1800s.brd - 94x70mm (short version).

Zip Archive - 14.89 kB - 05/05/2018 at 15:27

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nedo1802_v1_0.zip

Eagle v5.1 files for CPU module with 1801VM2 - 160x100mm.

Zip Archive - 100.76 kB - 05/02/2018 at 04:00

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cern_ohl_v_1_2.pdf

Open hardware license CERN OHL v.1.2.

Adobe Portable Document Format - 95.73 kB - 04/17/2018 at 08:14

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  • Justification for Robotics Module Challenge

    SHAOS06/03/2018 at 20:08 0 comments

    I submitted this project to "Robotics Module Challenge" as well and I think I need to show that it's possible to convert PDPii to a robot of some kind ;)

    As you can see I have enough equipment to do that - any interest from the public? :)

  • CPU module testing without memory

    SHAOS05/21/2018 at 05:56 0 comments

    As I already wrote before, CPU module alone could be used to test 1801VM2 CPUs - with manual clock (when user presses button periodically) and without memory (databus always returns all zeros). This board was tested today:

    This is video in 1080p60 mode:

    and this is a success! ;)

  • CPU module PCB built

    SHAOS05/13/2018 at 05:11 0 comments

    A few days ago I received 3 PCBs from OSHPark:

    and today built one of them:

    for testing purposes all ICs have sockets - now it's time to test :)

  • Live video of RAM module making

    SHAOS05/12/2018 at 04:49 5 comments

    Live video stream 1280x720 from my PowerPC G4 laptop ended - speed-up video is here:

    This is a result of almost 6-hour work:

    ZIP with SCH and BRD uploaded to Files

  • Live video of ROM module making

    SHAOS05/06/2018 at 03:56 11 comments

    I live streamed creation of ROM module board in Eagle v5 running in MacOS X 10.4 on the one of the latest PowerPC G4 laptops that I own since 2007 ;) 

    Later I edited archived videos to remove pauses and made it 8x faster:

    Results (ROM 64K board) added to GitHub and here in Files:

  • Board templates

    SHAOS05/05/2018 at 15:38 0 comments

    I added board templates here and at GitHub repository (moved to GitLab in June 2018)

    it's full size board with height 70mm to make sure it fits under the power supply in mini-ITX computer case. Schematics have just header in it and nothing else:


    Shorter version, that use only Q-bus part of BBQ-bus+ interface (and fits into limits of Eagle v5 free edition):

    Schematics:

    Here you need to do address latch on your own, but PCB might be much smaller.

    Also in both cases if you don't use DMA or interrupts then you should connect BDMGI to BDMGO and BIAKI to BIAKO to make sure those daisy chains are keep functioning for the next boards connected to backplane after your board.

  • CPU module PCB ordered

    SHAOS05/02/2018 at 04:05 5 comments

    CPU module v1.0 was ordered through OSHPark:


    SCH and BRD files for Eagle v5 attached in Files section:
    https://cdn.hackaday.io/files/673692882315296/nedo1802_v1_0.zip

    and also uploaded to GitHub and later moved to GitLab:

    https://gitlab.com/shaos/pdpii

  • Working on CPU module

    SHAOS04/27/2018 at 06:36 0 comments

    1st module that I'm trying to create right now is CPU module with 1801VM2 onboard - I'm buffering everything (VM2 pins are very weak) and also this module has address decoding and indication for some important signals:

    CPU might be clocked by button, by TTL oscillator or by external clock (CLCI):

    Board will look like this (160x100 mm):

    It could be vertically inserted into mini-ITX backplane (not yet designed), but also might be used as a standalone VM2 tester

    BTW thanks to OSHPark for rendering this image ;)


    Printed it on paper to see how it may fit into mini-ITX computer case:

    As you can see CPU module is a little too high - power adapter will not allow to put it in most of the slots of mini-ITX backplane but if it will be the last board (as pictured above), it should be ok, because power adapter is a little bit shorter than mini-ITX board and we have some free space there on the side...

  • Possible videomodes

    SHAOS04/23/2018 at 09:20 0 comments

    Ideally I want to be able to run not only text-oriented PDP-11 software, but also system and gaming software from Soviet BK-0011M home computer that had 512x256 monochrome video mode and 256x256 4-color video mode (with some predefined palettes). Output might be VGA with 2 resolutions - 640x350 (to display mentioned above 512x256 and 256x256 with some border space around) and 640x400 (to display "extended" video modes 640x200 monochrome and 320x200 4-color when every line will be shown twice by hardware) - both resolutions have the same pixelclock 25.175 MHz and the same field frequency 70.086 Hz. These are some photoshopped examples:

    It was existing BK-0010 and BK-0011M software and now - new modes:

    640x200 monochrome (first) and 320x200 4-color (second)

    It's even possible to create very tricky videomode for 320x200 where every line may have its own 4-color palette...

  • Peculiar VM2 pipelining

    SHAOS04/23/2018 at 07:18 0 comments

    First PDP-11 compatible chip in USSR named 1801VM1 was slow, so Soviet engineers decided to add instruction pipelining into next 1801VM2 to make it faster (microcode became so sophisticated that they left a few unnoticed holes in VM2 microcode which were patched only in later CMOS version 1806VM2). This is how I found out how VM2 pipelining works:

    I wanted to know how many cycles this subroutine from Elektronika MK-85 will take (it's display clean procedure):

    ; clear screen
    
    decimalnumbers
    
       org 0
    
    .word   L0A34
    .word   0
    
       org 0A34h
    ; 0A34:
    L0A34:   mov   #80h,r0
    ; 0A38:
    L0A38:   inc   r0
    ; 0A3A:
    L0A3A:   clrb   07F80h(r0)
    ; 0A3E:
       clrb   (r0)+
    ; 0A40:
       bit   #7,r0
    ; 0A44:
       bne   L0A3A
    ; 0A46:
       cmp   r0,#0E0h
    ; 0A4A:
       bcs   L0A38
    ; 0A4C:
    make_mk85_rom "clr.bin",32768

    Program is compilable by PDP11ASM utility, but in my experiment I set every word manually by switches every time when new address is shown on address LEDs:

    0003 0000                            decimalnumbers
    0005 0000                               org 0
    0007 0000 005064                     .word   L0A34
    0008 0002 000000                     .word   0
    0010 0004                               org 0A34h
    0012 0A34 012700 000200              L0A34:   mov   #80h,r0
    0014 0A38 005200                     L0A38:   inc   r0
    0016 0A3A 105060 077600              L0A3A:   clrb   07F80h(r0)
    0018 0A3E 105020                        clrb   (r0)+
    0020 0A40 032700 000007                 bit   #7,r0
    0022 0A44 001372                        bne   L0A3A
    0024 0A46 020027 000340                 cmp   r0,#0E0h
    0026 0A4A 103766                        bcs   L0A38

    Below addresses are hexadecimal, but opcodes and arguments - octal (as usual for PDP-11):

    0A34h 012700 mov #80h,r0 <<< 1st half (actual instruction opcode) took 8 cycles
    0A36h 000200 <<< then 2nd half (argument 0x0080) took another 12, so it's 20 cycles total
    0A38h 005200 inc r0 <<< increment of R0 took 8 cycles (now R0=0x0081)

    this is beginning of the loop:

    0A3Ah 10506clrb 07F80h(r0) <<< then clear BYTE memory location with offset R0 - 1st half took 8 cycles
    0A3Ch 077600 <<< 2nd half (argument 0x7F80) took another 28 cycles (because it then goes to address 0x8001 to read word and then write modified word back), so it's 36 cycles total

    at this point everything is logical and as expected, but then I observed a chaos:

    0A3Eh 105020 clrb (r0)+ <<< it should clean BYTE by address R0 with post-increment, so we should expect read-modify-write from/to 0x0081 (current R0 value) - reading of opcode took 8 cycles
    BUT THEN IT DOESN'T GO TO READ-WRITE FROM MEMORY - it goes to fetch next opcode!
    0A40h 032700 bit #7,r0 <<< read next opcode in 8 cycles

    then we go to read argument 0x0007, right? WRONG! then it goes to finish previous command and perform READ-WRITE on address 0x0081! another 18 cycles

    0A42h 000007 <<< and now we read argument 0x0007 - another 12 cycles
    0A44h 001372 bne L0A3A <<< conditional branching opcode - 8 cycles to read
    0A46h 020027 cmp r0,#0E0h <<< and then it reads NEXT OPCODE (just in case?) in 8 cycles, but this instruction will NOT be executed, because conditional branching was successful, so CPU doesn't bother to read argument 0x00E0 of that "just in case" instruction:

    0A48h 000340 <<< ignored
    and jump - address indication shows 0x0A3A now...
     
    So one run through loop is taking 36+26+20+8+8=98 cycles of CLCI - it's clearing 2 bytes in different parts of memory with post-increment of R0 and test that 3 less significant bits of R0 are not 0 to decide if it needs to continue (loop is intended to run through 96 bytes with skipping every 8th one).

    Per information from one knowledgeable person:

    • 1801VM2 without dots on the package is capable of doing 12.5 MHz of CLCI
    • 1801VM2 with 1 dot was tested on the factory with 10 MHz of CLCI
    • 1801VM2 with 2 dots is worst from the series that was passed only 8 MHz test (but they recommend not go higher than 6 MHz for this kind)

    Now you can estimate performance of your chip: 10-MHz one can do 1.25 million simple 8-cycle instructions per second and...

    Read more »

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Discussions

Eugene Zaikonnikov wrote 06/14/2018 at 11:30 point

Cera package (white) VM2s come in several grades, as much of Soviet electronics. 1st grade is plain package, one dot under the name is 2nd grade, two dots - 3rd grade. Have to be downclocked accordingly to operate.

  Are you sure? yes | no

SHAOS wrote 06/14/2018 at 13:51 point

I was not able to run ceramic VM2 reliably even on ~0 Hz ;)

  Are you sure? yes | no

jbroxson wrote 04/27/2018 at 21:26 point

...also since the 1801's are a bit hard to find, it might be interesting to build a mod around an FPGA (as Modzer0 mentioned)..  here is a project at OpenCores that would go a long ways to helping: https://opencores.org/project/w11

  Are you sure? yes | no

SHAOS wrote 04/28/2018 at 01:21 point

Actually 1801 is much easier to find than anything else PDP-11 related ;)
Three CPUs from this family 1801VM1 (SMD), 1801VM2 (with his CMOS version 1806VM2 in SMD package) and 1801VM3 (in DIP64!!!) are easily purchasable (but I'm currently focusing on black KR1801VM2)

Math co-processor 1801VM4 is not so easy to find - the same as more advanced Soviet PDP-11 chips - especially if they are still in use by Russian military...

  Are you sure? yes | no

Modzer0 wrote 04/28/2018 at 01:34 point

The only ones I've seen on ebay at the moment are KM1801VM2. That's from the US, other locations may have different results.

  Are you sure? yes | no

SHAOS wrote 04/28/2018 at 01:54 point

As I already said below - I bought all black ones already :)

I did this on impulse when I realized that all black VM2s that I have are running successfully through my tests ;)

So I will include tested VM2 with every kit if I will sell the kit :)

White ones (KM1801VM2 from late 80s) are still available on eBay, but I have problems to make them work reliably (may be I'm doing something wrong - for example handshake has to be delayed for earlier exemplars and so on - I'll do more experiments later with CPU board that I'm drawing right now)

P.S. Also I think it should be relatively easy to design CPU boards for PDPii that has other PDP-11 compatible processors on it - like T11, 1801VM1, 1806VM2 or even 1801VM3 (but I should decide what to do with 6 extra address lines)

  Are you sure? yes | no

SHAOS wrote 04/28/2018 at 02:09 point

Hm, 1801VM1, 1806VM2 and 1801VM3 all disappeared :(

eBay currently have only 2 lots for white 1801VM2s - from Russia and from Romania

  Are you sure? yes | no

SHAOS wrote 05/02/2018 at 01:22 point

Now I see a lot of J11 on eBay (for some reason I didn't see them before), but they are pricey ;)

  Are you sure? yes | no

Modzer0 wrote 04/28/2018 at 01:27 point

That's no longer maintained on opencores. The github w11 project is the most current. https://github.com/wfjm/w11

That is a SOC core however. It still fits on a midrange Artix-7 FPGA. If we isolated the CPU logic it should be possible to fit it on an even smaller FPGA, hopefully one with a QFN/QFP package to make it solderable by more people.  There are some FPGA DIP dev boards that would make things easier for everyone if the IP core can be fit on those chips.

There are some NOS J-11 "Jaws" CPUs still in their original packaging available on ebay. They're not exactly cheap at just under $100 USD, but it doesn't take much to get it running.

https://www.ebay.com/itm/DEC-Digital-DCJ11-AE-CPU-57-19400-09-/142036805152?hash=item21120da620

I bought some in another listing as things featured on HaD tends to get associated items bought up.

My justification to myself being I can hook one up and run it in lockstep with any FPGA solution to verify cycle accurate execution.

  Are you sure? yes | no

jbroxson wrote 04/27/2018 at 21:20 point

I may have missed it, but have you thought about how to expose "Front Panel" controls? Since you are targeting an ITX case, you could make a PCB that would fit a 5.25 slot on the front of the case and allow for the full blinken-lights experience...

  Are you sure? yes | no

SHAOS wrote 04/28/2018 at 01:13 point

I'll think about it

  Are you sure? yes | no

SHAOS wrote 04/28/2018 at 01:56 point

Actually my mini-ITX case doesn't have front slots at all :)

  Are you sure? yes | no

SHAOS wrote 05/01/2018 at 01:28 point

I have another mini-ITX case that is a little longer - that one actually has 5-inch bay, but I better put CD-ROM there ;)

  Are you sure? yes | no

don.vukovic wrote 04/27/2018 at 00:42 point

It seems that all the chips on ebay have already been taken.
Shame.

  Are you sure? yes | no

SHAOS wrote 04/27/2018 at 06:30 point

Yes, it looks like I bought them all :(

  Are you sure? yes | no

Modzer0 wrote 04/18/2018 at 03:10 point

The J-11 is hard to find at a reasonable price. The Russian chips work but be sure to leave space for a heatsink as they get rather hot. I have the datasheets on those if you need them, in Russian, but the pinouts can be identified.

  Are you sure? yes | no

SHAOS wrote 04/18/2018 at 03:24 point

Thank you, but I have all information already and I can read Russian ;)
I even tried successfully run black 1801VM2s manually (step by step) - I'll soon document my experiments here...

  Are you sure? yes | no

Modzer0 wrote 04/18/2018 at 23:18 point

I'm working on learning more Russian. I am a fan of old computer systems. The older Russian designs is something I haven't had the opportunity to examine in depth. The PDP-8 and PDP-11 are two of my favorite architectures, and I know there were clones produced. I've restored systems and built replacement boards using FPGAs to repair and make spare parts for a couple of old systems that are still running RT-11 on a contract. I unfortunately can't share those as the client owns the designs and IP. I also don't want to make them angry as I had a lot of fun working with them. When you get your backplane specifications finished I look forward to designing some boards for it if I manage to find some free time.

  Are you sure? yes | no

SHAOS wrote 04/19/2018 at 01:02 point

Great, I'll probably will need your advice in very near future, because I'm familiar with PDP-11 instruction set only in scope of Russian machines build around PDP-11 compatible processors like Elektronika MK-85 (I own this one since 1991), Elektronika BK-0011M (recently bought one on eBay) and DVK-2 (first computer that I actually used in 1990 to learn coding in high school) and those machines were NOT clones of PDP-11 machines (no RT-11 or something was running on them). Total clones of PDP-11 line sure existed in Russia too (like Elektronika 60 and 100), but I never saw them and not even knew that they existed until like a few years ago...

P.S. Actually nobody told us in that time that 1801-series of microprocessors was PDP-11 compatible - I found out about that much later on Internet :)

  Are you sure? yes | no

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