The Low Voltage Translator Block Diagram:
The Low Voltage Translator translates low voltage into your multimeter (or oscilloscope) voltage range
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The Low Voltage Translator Block Diagram:
This project log explains about PCB layout and design consideration of The Low Voltage Translator. To save costs and optimize the design, we will use the PCB as well as the component circuit and box panel of The Low Voltage Translator inspired from The uCurrent Project . Making IO panel on the box case is costly and time-consuming for small-scale production like in this project. The connection between separated circuit and IO panel also can add noise significantly from the environment . Figure 1 is the example of using PCB as well as component circuit and box panel in The uCurrent project.
Figure 1. Top layer PCB containing the circuit (left) and bottom layer PCB as IO panel box (right)
We will replace the plastic box on Figure 1 with the metal box to reduce noise by using Faraday Cage effect for shielding against EMI . We also can keep the metal shield on the panel by making a ground plane on the PCB layer dedicated as an IO panel like on the right picture in Figure 1. We also adapt uCurrent for uses of the battery without a switch-mode regulator for reducing noise. But, this project using two battery for split supply instead of op amp follower like in the uCurrent to overcome output impedance of the op-amp.
For designing a PCB, we are using Circuit Maker, Altium version for open source PCB design. So, you can put this project design in your Circuit Maker using the keyword "The Low Voltage Translator". Figure 2 and Figure 3 contains the top layer and the bottom layer of The Low Voltage Translator design.
Figure 2. Top layer PCB design
The top layer PCB design used for all of circuit network. Trace in the top layer is red. All the trace in the top layer made as short as possible to minimize impedance . The long trace, the IO signal trace, and the power trace made by using the polygon to minimize trace impedance . The via only connecting ground on the top layer and ground plane on the bottom layer to minimize impedance. The purpose of minimizing impedance in this design is to reduce noise pickup on the trace.
To minimize trace reflection, we are using rounding shape on the corners trace which are better than 45-degree corners .
Figure 3. Bottom Layer PCB design
Trace in the bottom layer is blue. Trace In the bottom layer PCB only contain ground plane for connecting ground on the top layer and for shielding uses . Besides that, the ground plane also minimize loop area which have the same function as the antenna that vulnerable against EMI. View of the 3D model of the top layer and the bottom layer can be seen on the Figure 4 and Figure 5.
Figure 4. 3D model of top layer PCB design
Figure 5. 3D model of bottom layer PCB design
This project log is explaining about proposed schematics of The Low Voltage Translator and their simulation performance on TINA-TI SPICE. The proposed schematics of The Low Voltage Translator are shown in Figure 1 and Figure 2.
Figure 1. 1st version of The Low Voltage Translator Amplifier
Figure 2. 2nd version of The Low Voltage Translator Amplifier
Because we only using low resistance value on the both schematic, we only considering input voltage noise and neglected the input current noise of the amplifier . The total Gain in the 1st version amplifier is 1000 and the 2nd version is 10000.
The parallel configuration of the op-amp can reduce noise with the factor of 1/(sqrt(total of the parallel op-amp)) . Since 1st version amplifier containing 4 parallel op-amps and 2nd version amplifier containing 3 parallel op-amps, so the 1st version winning the parallel effect for reducing noise.
In multiple stage amplifier configuration, the first stage of the amplifier add noise more significantly . Therefore, in 2nd version amplifier 3 op amp on the first stage is parallel to reduce voltage noise in the first stage of the amplifier. The higher order low pass filter can reduced noise than lower order filter because the noise voltage in input op amp is white and can be reduced with more narrow bandwidth . The multiple stage configuration amplifier like in the 2nd version enabling to apply higher order filter than in the single stage amplifier configuration like in 1st version. So, the 2nd version winning the filter effect for reducing noise with the 3rd order low pass filter.
To know about the best-proposed design, we simulate them in TINA-TI. Before doing the simulation, we make the identical model for JRC4580 in TINA-TI. The voltage noise density of the JRC4580 referring to its datasheet and the JRC4580 model in TINA-TI is shown in Figure 3 and Figure 4.
Figure 3. Noise voltage input density of JRC4580 from its datasheet
Figure 4. Noise voltage input density of JRC4580 model in TINA-TI
The Figure 3 and Figure 4 shows that the model of JRC4580 in TINA-TI is identical enough to its datasheet. The result simulation is the plot of RMS Noise voltage output vs Frequency on the 1st and the 2nd version of The Low Voltage Translator amplifier which is shown in Figure 5 and Figure 6.
Figure 5. Simulation result of The 1st version amplifier schematic
Figure 6. Simulation result of The 2nd version amplifier schematic
The magnitude of the vertical axis in Figure 5 and Figure 6 is Total voltage noise output amplifier in RMS. We need to divide those value with the gain of each amplifier to get voltage noise input in RMS. The result is 48uV/1000 = 48 nV RMS for the 1st version and 370uV/10000 = 37 nV RMS for the 2nd version.
The 2nd version amplifier is winning because of combining all method to reducing noise. Because the meaning of VRMS of noise is the probability, we will use the approximation of 6 x VRMS = Voltage Noise peak to peak with 99.7% probability . So, the value of Voltage noise input peak to peak of 2nd version amplifier is 6 x 37nV= 222 nV peak to peak. Since we want to detect 10uV, the 222 nV is about 2.5%. In the next progress, we will use this data to compare with the data from the prototype of The Low Voltage Translator using the 2nd version of schematic.
Like the UCurrent, the heart of the design of The Low Voltage Translator is the amplifier . To choose the best amplifier for this purposes, we need to know the priority of the amplifier specification needed.
The Low Voltage Translator wants to detect small signal until 10 uV. It means that we need the amplifier with input voltage noise peak to peak is 5% of 10uV to get 5% error of measurement. So, the next step is considering the best amplifier from low noise operational amplifier family.
I have discussed with some expert about the best low noise op-amp used for this purposes and they suggest me the OPA211. This is the figure of OPA211 voltage noise density referring to its datasheet . We also neglect the current noise density of amplifier because we will use relative low resistance value of the resistors in the design .
Figure 1. OPA211 input voltage noise density.
Referring to Figure 1, OPA211 has 1.1 nV/(sqrt(Hz)) voltage noise density, one of the lowest voltage noise density op amp in the world. Besides that, total harmonic distortion (THD) of OPA211 also excellent, 0.00015%, one of the lowest THD op amp in the world.
The alternative for OPA211 is JRC4580 which also has low voltage noise density. This is the figure of JRC4580 voltage noise density referring to its datasheet .
Figure 2. JRC4580 input voltage noise density.
Referring to Figure 2, JRC4580 has 5 nV/(sqrt(Hz)) voltage noise density, it is good but slightly higher than OPA211. Besides that, total harmonic distortion (THD) of JRC4580 also good, 0.0005%, slightly larger than OPA211. Besides that, JRC4580 has the cheaper price than OPA211. It makes JRC4580 is preferable to first version prototype of The Low Voltage Translator to reduce the risk of failure.
The input voltage noise density value must be calculated to get input voltage noise RMS. From input voltage noise RMS, we can calculate the final result, the input voltage noise peak to peak. It must meet error specification of The Low Voltage Translator which is 5% of 10uV. In the next project log, we will propose the design schematic and calculating input voltage noise peak to peak to meet the specification of The Low Voltage Translator.
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