we could schrink the Cortex-M0 core to fit into the smallest target silicon available?
We could then take standard GCC and compile code that runs in CHIP made by YOU!
Smaller than grain of sand, priced at 1 USD.
Nah, this is not possible !?
- Optimized bit-serial implementation of Cortex-M0 ISA
- Resource usage
- LUT4 <= 500
- Flip-Flop <= 500
- block RAM primitives < 4 (not counting program and data memories)
- clocks per instruction < 128
The resource usage should be less than 50% of Lattice HX1K or XO2-1200 FPGA