The NEORV32 Processor is a customizable microcontroller-like system based on a RISC-V-compliant CPU.
It is intended as auxiliary processor within larger SoC designs or as stand-alone custom microcontroller. The processor provides common peripherals like GPIO, aerial interfaces, timers, external bus interface and embedded memories. All features beyond the base CPU are optional and can be configured via VHDL generics. Most of the peripherals are recycled from the NEO430 processor.
The project comes with a complete software ecosystem that features core libraries for high-level usage of the provided functions and peripherals, application makefiles , a run-time environment and several example programs.
The project is intended to work "out of the box " - just synthesize the provided test setup, upload it to the FPGA board of choice and start playing with the NEORV32.
- RISC-V-compliant rv32i CPU with optional C, E, M, U, Zicsr,
Zifencei and PMP (physical memory protection) extensions
- Passes the official RISC-V compliance tests
- GCC-based toolchain (pre-compiled rv32i and rv32e toolchains available)
- Application compilation based on GNU makefiles
- Doxygen-based documentation of the software framework; deployed on GitHub pages
- Full-blown datasheet (pdf)
- Completely written in behavioral, platform-independent VHDL – no primitives, macros, etc.
- Fully synchronous design, no latches, no gated clocks
- Small hardware footprint and short critical path for easing timing closure
- Highly configurable CPU and processor setup
- Tested on Xilinx, Intel and Lattice FPGAs
- From zero to main(): Completely open source and documented.
- Plain VHDL without technology-specific parts like attributes, macros or primitives.
- Easy to use – working out of the box.
- Clean synchronous design, no wacky combinatorial interfaces.
- Be as small as possible – but with a reasonable size-speed trade-off.
- The processor has to fit in a Lattice iCE40 UltraPlus 5k FPGA running at 20+ MHz.