The NEORV32 Processor is a customizable microcontroller-like SoC based on the NEORV32 RISC-V-compliant CPU.
It is intended as auxiliary processor within larger SoC designs or as stand-alone custom microcontroller. The processor provides common peripherals like GPIO, serial interfaces, timers and embedded memories. All features beyond the base CPU are optional and can be configured via VHDL generics.
The project comes with a complete software ecosystem that features core libraries for high-level usage of the provided functions and peripherals, application makefiles , a run-time environment, several example programs and even a freeRTOS port.
The project is intended to work "out of the box " - just synthesize the provided test setup, upload it to the FPGA board of choice and start playing with the NEORV32.
Also check out the project boards on GitHub to see what I'm currently working on and which further features are in the pipeline.
- online data sheet / documentation (based on asciidoc)
- completely described in behavioral, platform-independent VHDL - no primitives, macros, attributes, etc.
- fully synchronous design, no latches, no gated clocks
- be as small as possible (while being as RISC-V-compliant as possible) – but with a reasonable size-performance trade-off (the processor has to fit in a Lattice iCE40 UltraPlus 5k low-power FPGA running at 22+ MHz)
- from zero to printf("hello world!"); - completely open source and documented
- easy to use even for FPGA/RISC-V starters – intended to work out of the box
- tested on real hardware (Xilinx, Intel and Lattice FPGAs)
- NEORV32 CPU: RISC-V-compliant rv32i CPU (passes the official RISC-V compliance tests) with optional extensions:
- A - atomic memory access instructions
- B - bit manipulation instructions (Zbb subset)
- C - compressed instructions (16-bit)
- I - base integer instruction set
- E - embedded register file (reduced register file size)
- M - integer multiplication and division hardware
- U - less-privileged user mode
- X - NEORV32-specific CPU extensions
- DB - CPU debug mode
- Zfinx - Single-precision floating-point extension
- Zicsr - Control & status registers (allows interrupts and exceptions)
- Zifencei - Instruction stream synchronization (e.g. for self-modifying code)
- PMP - Physical memory protection
- HPM - hardware performance monitors
- Interrupts: RISC-V timer, software & external interrupts + 16 fast interrupts + 1 non-maskable interrupt
- NEORV32 Processor: Full-scale RISC-V microcontroller system / SoC with optional and configurable modules:
- embedded memories (instructions/data/bootloader, RAM/ROM) and caches
- timers (watch dog, RISC-V-compliant machine timer)
- serial interfaces (SPI, TWI, UARTs, ...)
- general purpose IO and PWM
- dedicated NeoPixel(TM) LED interface
- external bus interface (Wishbone / AXI4)
- on-chip debugger with JTAG interface (compatible to OpenOCD and gdb)
- Software framework:
- core libraries for high-level usage of the provided functions and peripherals
- application compilation based on GNU makefiles
- GCC-based toolchain (pre-compiled toolchains available)
- bootloader and runtime environment
- several example programs
- doxygen-based documentation: available online on GitHub pages
- FreeRTOS port available
- Example setups for various FPGA boards to get you started
- Arty A7 (Xilinx Artix-7)
- UPduino (Lattice ice40 UltraPlus)
- DE0-nano (Intel Cyclone IV)
- open-source synthesis setup for UPduino based on GHDL, Yosys & nextPNR