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The NEORV32 RISC-V Processor

An easy-to-use, customizable, lightweight and open-source 32-bit RISC-V microcontroller/CPU written in platform-independent VHDL.

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A small and highly customizable full-scale rv32[i/e][m][a][c][b][u][Zfinx][Zicsr][Zifencei]+[PMP][HPM] RISC-V CPU and SoC written in platform-independent VHDL.

The project itself and all sources including the documentation is available on GitHub (https://github.com/stnolting/neorv32) and released under the BSD 3-Clause "New" or "Revised" License.

The NEORV32 Processor is a customizable microcontroller-like SoC based on the NEORV32 RISC-V-compliant CPU.

It is intended as auxiliary processor within larger SoC designs or as stand-alone custom microcontroller. The processor provides common peripherals like GPIO, serial interfaces, timers and embedded memories. All features beyond the base CPU are optional and can be configured via VHDL generics.

The project comes with a complete software ecosystem that features core libraries for high-level usage of the provided functions and peripherals, application makefiles , a run-time environment, several example programs and even a freeRTOS port.

The project is intended to work "out of the box " - just synthesize the provided test setup, upload it to the FPGA board of choice and start playing with the NEORV32.

The project is hosted on GitHub. The project's change log can be found here.

Also check out the project boards on GitHub to see what I'm currently working on and which further features are in the pipeline.

NEORV32 Processor (SoC)

Key Features

  • online data sheet / documentation (based on asciidoc)
  • completely described in behavioral, platform-independent VHDL - no primitives, macros, attributes, etc.
  • fully synchronous design, no latches, no gated clocks
  • be as small as possible (while being as RISC-V-compliant as possible) – but with a reasonable size-performance trade-off (the processor has to fit in a Lattice iCE40 UltraPlus 5k low-power FPGA running at 22+ MHz)
  • from zero to printf("hello world!"); - completely open source and documented
  • easy to use even for FPGA/RISC-V starters – intended to work out of the box
  • tested on real hardware (Xilinx, Intel and Lattice FPGAs)
  • NEORV32 CPU: RISC-V-compliant rv32i CPU (passes the official RISC-V compliance tests) with optional extensions:
    • A - atomic memory access instructions
    • B - bit manipulation instructions (Zbb subset)
    • C - compressed instructions (16-bit)
    • I - base integer instruction set
    • E - embedded register file (reduced register file size)
    • M - integer multiplication and division hardware
    • U - less-privileged user mode
    • X - NEORV32-specific CPU extensions
    • DB - CPU debug mode
    • Zfinx - Single-precision floating-point extension
    • Zicsr - Control & status registers (allows interrupts and exceptions)
    • Zifencei - Instruction stream synchronization (e.g. for self-modifying code)
    • PMP - Physical memory protection
    • HPM - hardware performance monitors
    • Interrupts: RISC-V timer, software & external interrupts + 16 fast interrupts + 1 non-maskable interrupt
  • NEORV32 Processor: Full-scale RISC-V microcontroller system / SoC with optional and configurable modules:
    • embedded memories (instructions/data/bootloader, RAM/ROM) and caches
    • timers (watch dog, RISC-V-compliant machine timer)
    • serial interfaces (SPI, TWI, UARTs, ...)
    • general purpose IO and PWM
    • dedicated NeoPixel(TM) LED interface
    • external bus interface (Wishbone / AXI4)
    • on-chip debugger with JTAG interface (compatible to OpenOCD and gdb)
  • Software framework:
    • core libraries for high-level usage of the provided functions and peripherals
    • application compilation based on GNU makefiles
    • GCC-based toolchain (pre-compiled toolchains available)
    • bootloader and runtime environment
    • several example programs
    • doxygen-based documentation: available online on GitHub pages
    • FreeRTOS port available
  • Example setups for various FPGA boards to get you started
    • Arty A7 (Xilinx Artix-7)
    • UPduino (Lattice ice40 UltraPlus)
    • DE0-nano (Intel Cyclone IV)
    • open-source synthesis setup for UPduino based on GHDL, Yosys & nextPNR
    • ...

NEORV32.pdf

Version 1.5.5.0

Adobe Portable Document Format - 3.76 MB - 05/11/2021 at 12:56

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  • An IEEE-754 Floating-Point Unit for the NEORV32

    Stephan03/25/2021 at 13:30 0 comments

    After some struggles (and nightmares!) understanding the IEEE-754 specs and several FPU IP data sheets I have nearly finished implementing the NEORV32 floating point extension.

    I have decided to implement the RISC-V Zfinx floating-point extension rather than the standard F extension to focus on size-optimization. Zfinx uses the standard integer register file x instead of a dedicated floating-point register file f, which is required by the F extension.

    Read more »

  • A native NeoPixel interface for the NEORV32

    Stephan02/25/2021 at 21:14 0 comments

    The cool thing of having a soft-core processor is you can add exactly the features you are wishing for. Some days ago I got a hint on the WS2812 LEDs, which are used in Adafruit's awesome NeoPixels. The interface is quite heavy when it comes to timing constraints and I figured out that some platforms struggle with it.

    WS2812 Protocol

    In summary, the WS2812 interface is based on a single signal carrying an asynchronous data protocol. It uses a fixed 800KHz frequency and modifies the duty cycle to carry the '0' and '1' bits.

    T0H0.4µs
    T1H0.8µs
    T0L0.85µs
    T1L0.45µs
    T_total1.25µs
    RESET (data "strobe")
    +50µs

    Timings and diagram were taken from the Adafruit NeoPixel Überguide.

    Small mikrocontrollers like AVRs can tackle the hard timing (for example using the FastLED library), but might need some inline assembly to keep up with it. Also, the image is better off being stored entirely somewhere in memory (consuming precious RAM) since real time rendering might crash in-time bit-banging. Things are getting even more complicated when pairing the hard timing constraints with setups using interrupts...

    More powerful platforms like the Raspberry PI do have the processing power to bit-bang the interface, but they also might run into real-time problems when OS interrupts kick in.

    In summary, pure-software based approaches come with more than just a few issues. So, why not create a dedicated hardware interface that takes all the critical interface work from us?

    Read more »

View all 2 project logs

  • 1
    Get the NEORV32 from GitHub

    Use git clone from your console:

    git clone https://github.com/stnolting/neorv32.git

    Alternatively, you can download the repository as *.zip archive or download a specific release.

  • 2
    Get the toolchain

    You can either build the toolchain by yourself using the official RISC-V-GNU-Toolchain repository or you can download the toolchain(s) I am using as pre-built binaries from GitHub.

  • 3
    Start playing

    Follow the guides in the NEORV32 datasheet for:

    • installing the toolchain
    • creating and synthesizing a new HDL project
    • communicating with the NEORV32 bootloader
    • compiling an example application
    • uploading and running it on the processor

View all 3 instructions

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Discussions

initrd wrote 02/26/2021 at 02:57 point

Interesting project. From your Github page,

"This project is not affiliated with or endorsed by the Open Source Initiative (https://www.oshwa.org / https://opensource.org)." I notice it uses: BSD 3-Clause

I am curious if it is similar to http://solderpad.org/licenses/SHL-0.51/ from https://pulp-platform.org/

  Are you sure? yes | no

Stephan wrote 02/27/2021 at 17:47 point

BSD 3-clause is a very simple and quite permissive license and it has become pretty common among open-source HDL designs. I have never really thought about SHL - seems like I have to check that out ;)

  Are you sure? yes | no

initrd wrote 02/27/2021 at 17:52 point

I recently read about some of the hardware licenses, since I was "shopping" for my own platform. One of Pulp platform's researchers wrote an interesting article on the various licenses here: "You can find the article on pages 192-197 of the HIPEAC Vision 2021." from https://pulp-platform.org/latestnews.html

Edit: it's a 111MB file, so I've made just a 6-page version: https://cdn.hackaday.io/files/1777167603401344/192-197%20-%20Copy.pdf The full file works better in a standalone PDF reader like SumatraPDF- browser based PDF readers don't work well with large files.

  Are you sure? yes | no

ML wrote 02/16/2021 at 16:47 point

Wow! Great project to enter into the Risc-V world. 

Synthesis time is negligible,  the datasheet and documentation help to jump-in.

After passing over a few super-complex risc-v projects, I will use this one for further exploration.

  Are you sure? yes | no

Stephan wrote 02/17/2021 at 17:24 point

Thank you very much! ;)

Ease of use was one of the main ideas behind the project.

  Are you sure? yes | no

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