To make the experience fit your profile, pick a username and tell us what interests you.
The big picture in IPI BD:
Visible are the ARM CortexA9 hard core, and blocks for Audio, Camera and HDMI Display
The audio block, is implemented based on IP compatible to Analog devices SPDIF IP Core, so we can reuse eixsting drivers. The IP Core has been modified to expose not SPDIF but AXI4-Stream as audio output interface, what is connectef to AXI4-Stream to PWM IP Core. Please note that this IP core is using Cortex A9 DMA channels, the DMA engine is not created in the FPGA.
HDMI Output is also rather simple, Xilinx Video DMA is used to to get framebuffer data from DDR memory, this video streami is converted to color format supported by Linux simple framebuffer drivers, and then it sent to HDMI serializer. VDMA init is done in the FSBL, also logo is loaded by first stage bootloader so it appeary very quickly during startup.
MIPI CSI2 camera processing path is bit longer, it is first converted from CSI2 signals into intermediate PPI Interface also defined by MIPI alliance as the MIPI PHY interface. PPI is then converted to AXI4-Stream. As next step the video data passes dual clock FIFO to move into system clock domain. Then the camera data is processed to convert RAW10 format into RGB. Before going to Xilinx VDMA IP Core the video data is resized so that it can directly be displayed on HDMI monitor.
Thats it folks.
Old story, but it is working nicely. Full video patch from camera to HDMI working.
It is so cool that in every place I have one zynqberry with demo with me I get robbed, that is have to leave the berry to the begger..
axi to HDMI TMDS IP core + Xilinx free IP Catalog cores, simple linux framebuffer, DivX player.
Resources: 12% LUT, 4% FF, zynq 7010
1) f32c with hdmi - working good work all, this just worked
2) linux booting, USB support working, ethernet working, i2c scan works find the mux, etc.
with some struggle hamsters hdmi test does give some image out :)
pictures and info coming soon, PCB are in our fab!
Coming soon, excited once more - first board where I can test CSI and DSI interface with FPGA!
With lowest cost ZYNQ device package some compromises are required:
1 Bidirectional DSI not possible - this is very maybe not needed anyway
2 Analog video output replaced by audio input in 3.5mm Jack
This setup yields in I/O Pin utilization of 100% nothing is left over but nothing is missing either
Become a member to follow this project and never miss any updates