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Analog Multiplexer Logic

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TimTim 04/10/2020 at 15:4613 Comments

Not all weird discrete logic has to be based on ancient components.

Most projects in discrete logic families focus on recreating ancient circuit styles (like RTL, DTL, DCTL or, as a bastard abberation, LTL) with the components that are still available today. It turns out that many of the specialized transistors are long gone. How about doing it the other way: Pick a minimal building block that is easily available today and base logic on that? 

Browsing distributor listings I found an interesting category of small devices: Analog switches and multiplexers.

Basic building Block: The 2:1 Multiplexer

An example of an 2:1 analog multiplexer is shown above. These are not digital devices, but actual analog switches. The connection between B and A will be low ohmic when it is active and assume a very high resistance when deselected. This means that it can be used in both directions.

There is an abundance of 2:1 switches available in very small SOT-363 packages (above) from different sources for prices that rival that of discrete transistors. A short listing of some of the devices I found on LCSC is in the table below:

PartManufacturerPrice (100+)
NC7SB3157On Semi$0.046
74LVC1G3157Diodes Incorporated$0.037
74LVC1G3157Nexperia$0.048
SGM3157YC6SGMICRO
$0.03
BL1551Shanghai Beiling$0.03
CH443KJiangsu Qin Hang$0.036
SGM3157Youtai Semiconductor Co$0.036


Spice Model


Unfortunately I was not able to find any spice model of these devices that is suitable for LTspice. So I made my own behavioral model as shown below, next to the entity symbol. Many parasitics are not considered here. Neither is the delay that the control logic is causing, so it can only be seen as a crude approximation.


Note the biasing resistor on the output, which is very important to prevent LTspice from getting stuck in a metastable state. Spice does not really like switches...

Building basic logic gates

Most basic two-input gates can be realized with one or two analog multiplexers. It's interesting to note that the MUX is more accomodating to positive logic. Inversions typically require adding an additional multiplexer.

Inverter

AND Gate

The OR gate can be realized in a very similar manner. NOR and NAND require an additional inverter.

XOR Gate

XOR can be realized by an multiplexer that selectes between an inverted and non-inverted version of the secondary input. XNOR is realized by swapping multiplexer inputs.

Latches

Latches are the achilles heel of any logic family. Building a latch with a digital multiplexer is actually fairly easy and can be done with a single multiplexer by routing the output back to one of the inputs. However, this is not so easy with analog multiplexers, as they only act as a switch without any buffering or amplification.

Instead, we will revert to a dynamic latch as shown below.

The first multiplexer acts as a path gate. If the clk is high, the input data will be routed to the output where the storage capacitor is charged. If the clk is low, the output will be connected to a floating input, so that the charge on the capacitor is held. The second multiplexer acts as an output buffer.

Obviously this is a bit tricky in operation as some of the charge will dissipate through leakage into the buffer control input and internal leakage in the multiplexer. A sufficiently high clock is required to allow cyclicated refreshing of the latch content.

The figure above shows simulation results of the latch in operation. Since loading of the capacitor causes a current surge on the input, spikes are seen on the input signal. Proper buffers and dimensioning of the storage capacitor is necessary.

Counter design

To verify the functionality in a more complex circuit, I designed an 8 bit counter in spice. You can see some of the output traces above. I hope that some of the transient spikes disappear once real-world parasitics are added.

Summary

This looks like a potential approach to build discrete logic from modern components. I have not yet tried real circuits, but will do so once I get around. The gate propagation delays could be quite acceptable as turn-on and turn-off times of the multiplexers listed above are in the sub 5ns range, according to their datasheets.

EDIT: Improved Latch

As Joan pointed out below, it is perfectly possible to turn the dynamic latch into a static one. This allows removing the capacitor. The circuit is basically the same as one would use with a digital multiplexer. However, since the analog switches don't have any gain in their signal path, we have to introduce a second switch that is used to buffer the signal and create gain in the hold loop. Circuit below.


Discussions

Dave Collins wrote 11/09/2021 at 22:18 point

This is really interesting, if it's not obvious already, I love projects that use components in non- traditional configuration to get results. :) 

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Yann Guidon / YGDES wrote 11/09/2021 at 22:26 point

MUX logic was used in the first Actel antifuse FPGA sur as the A1020 I used in 1996 and these were already obsolete, but so much fun to play with !

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Tim wrote 11/10/2021 at 09:40 point

But I don't think that was based on low cost discrete ICs ;)

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Yann Guidon / YGDES wrote 11/10/2021 at 09:48 point

@Tim  not yet ;-) Did you coerce yosis to handle these gates ?

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Tim wrote 11/10/2021 at 10:31 point

Yes, already synthesized and ordered the counter design in AMUX logic.

(see image in TTLer chat)

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joan lluch wrote 08/28/2021 at 09:44 point

You can avoid the capacitor on the Latch implementation by simply feeding the Q output back to the B0 input of the first multiplexer. When the CLK signal goes low, the second multiplexer gets latched by its own output through the first multiplexer. The internal capacitance and propagation delay of the second multiplexer keeps it stable during the brief switch of the first multiplexer.

This removes clock timing constraints and makes the design much cleaner, while still using one less component.

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Tim wrote 08/29/2021 at 13:28 point

Edit:


Joan, you are completely right, in that case the second MUX would provide gain the loop and the capacitor is not needed anymore. Looks like I was a bit too excited about dynamic latches to come up with this much more elegant and simpler solutions :)

Interesting, this makes this logic style quite... more

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joan lluch wrote 08/30/2021 at 07:51 point

Yes, that's exactly the point. We still need two MUXes so that one of them provides gain to both the output and feedback loop. 

By chaining together two D-latches like that, but having the B1, B0 inputs of the very first mux swapped, you can create a master-slave type D-Flip flop, reacting to rising clock edges, with just 4 components, i.e, the 4 muxes. 

Interestingly, "Relay Logic", which is ultimately what we can do with these 2:1 muxes, is more 'compact' than any other logic family, because there's plenty of 'out of the box' tricks that can be implemented with relays that are not possible with traditional logic gates

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Tim wrote 08/30/2021 at 08:46 point

I did a quick test using Yosys to synthesize a small CPU core to MUX2/NOT logic. Unfortunately it seems that ABC has some trouble with this and still needs NOR2 or NAND2.

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Tim wrote 11/23/2021 at 22:30 point

Great idea saving on the clock inversion by switching the inputs of the first MUX to form a 4 amux-DFF. Seems to work in spice, I will try this in real hardware as well :)

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Yann Guidon / YGDES wrote 11/24/2021 at 07:38 point

@Tim I'm waiting for your schematics and report on the next log ;-)

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Tim wrote 04/10/2020 at 15:51 point

I thought I should contribute something here. Fringe logic styles seemed to be a good topic.

Let me know what you think.

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Yann Guidon / YGDES wrote 04/11/2020 at 02:15 point

one word :

delicious :-)

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