Analog Multiplexer Logic

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TimTim 04/10/2020 at 15:462 Comments

Not all weird discrete logic has to be based on ancient components.

Most projects in discrete logic families focus on recreating ancient circuit styles (like RTL, DTL, DCTL or, as a bastard abberation, LTL) with the components that are still available today. It turns out that many of the specialized transistors are long gone. How about doing it the other way: Pick a minimal building block that is easily available today and base logic on that? 

Browsing distributor listings I found an interesting category of small devices: Analog switches and multiplexers.

Basic building Block: The 2:1 Multiplexer

An example of an 2:1 analog multiplexer is shown above. These are not digital devices, but actual analog switches. The connection between B and A will be low ohmic when it is active and assume a very high resistance when deselected. This means that it can be used in both directions.

There is an abundance of 2:1 switches available in very small SOT-363 packages (above) from different sources for prices that rival that of discrete transistors. A short listing of some of the devices I found on LCSC is in the table below:

PartManufacturerPrice (100+)
NC7SB3157On Semi$0.046
74LVC1G3157Diodes Incorporated$0.037
BL1551Shanghai Beiling$0.03
CH443KJiangsu Qin Hang$0.036
SGM3157Youtai Semiconductor Co$0.036

Spice Model

Unfortunately I was not able to find any spice model of these devices that is suitable for LTspice. So I made my own behavioral model as shown below, next to the entity symbol. Many parasitics are not considered here. Neither is the delay that the control logic is causing, so it can only be seen as a crude approximation.

Note the biasing resistor on the output, which is very important to prevent LTspice from getting stuck in a metastable state. Spice does not really like switches...

Building basic logic gates

Most basic two-input gates can be realized with one or two analog multiplexers. It's interesting to note that the MUX is more accomodating to positive logic. Inversions typically require adding an additional multiplexer.


AND Gate

The OR gate can be realized in a very similar manner. NOR and NAND require an additional inverter.

XOR Gate

XOR can be realized by an multiplexer that selectes between an inverted and non-inverted version of the secondary input. XNOR is realized by swapping multiplexer inputs.


Latches are the achilles heel of any logic family. Building a latch with a digital multiplexer is actually fairly easy and can be done with a single multiplexer by routing the output back to one of the inputs. However, this is not so easy with analog multiplexers, as they only act as a switch without any buffering or amplification.

Instead, we will revert to a dynamic latch as shown below.

The first multiplexer acts as a path gate. If the clk is high, the input data will be routed to the output where the storage capacitor is charged. If the clk is low, the output will be connected to a floating input, so that the charge on the capacitor is held. The second multiplexer acts as an output buffer.

Obviously this is a bit tricky in operation as some of the charge will dissipate through leakage into the buffer control input and internal leakage in the multiplexer. A sufficiently high clock is required to allow cyclicated refreshing of the latch content.

The figure above shows simulation results of the latch in operation. Since loading of the capacitor causes a current surge on the input, spikes are seen on the input signal. Proper buffers and dimensioning of the storage capacitor is necessary.

Counter design

To verify the functionality in a more complex circuit, I designed an 8 bit counter in spice. You can see some of the output traces above. I hope that some of the transient spikes disappear once real-world parasitics are added.


This looks like a potential approach to build discrete logic from modern components. I have not yet tried real circuits, but will do so once I get around. The gate propagation delays could be quite acceptable as turn-on and turn-off times of the multiplexers listed above are in the sub 5ns range, according to their datasheets.


Tim wrote 04/10/2020 at 15:51 point

I thought I should contribute something here. Fringe logic styles seemed to be a good topic.

Let me know what you think.

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Yann Guidon / YGDES wrote 04/11/2020 at 02:15 point

one word :

delicious :-)

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