21326 Results for "8-bit cpu"

MISC Core Already Sports 8 Instructions
Log from Kestrel Computer Project
NOP, LIT8, LIT16, LIT32, SBM, SHM, SWM, and SDM are implemented.NOP is the no-operation opcode, of course.LITx loads an x-bit literal onto the data stack.SxM stores a byte, half-word, word, for double-word value to memory.In a mere five hours of hacking,...

First working CPU run!
Log from RC2016/99: TI-99/4A clone using TMS99105 CPU
Got the CPU working. The video is very lame (shot on my iPhone - unfortunately low res). But the point is, the TMS99105 actually runs and executes instructions! CPU external clock is still 20MHz, so machine cycle time is 200 ns (runs at 5MHz).There are...

Accessing CPU Memory from Front Panel
Log from 8 Bit Computer Front Panel
Created a branch which simulates controlling a CPU memory from the Front Panel. Made the memory an 8KB, Dual Port SRAM in the CPU. Able to read/write the memory.It works! Front Panel controls are: The bottom 8 Pushbuttons/LEDS control d0-d7 of the SRAM....

Interrupts now work
Log from TMS9900 compatible CPU core in VHDL
One more feature done! Now the CPU core supports interrupts, leaving the major missing features to MPY and DIV instructions - and a whole bunch of debugging.The CPU core now has 3 more I/O signals:int_req : in STD_LOGIC; -- interrupt request, active...

CPU redevelopment
Log from One instruction VGA computer
I will first focus on redesigning the CPU. I don't think the design will change much from a high block level, but most of the chips will be different. I had to make a couple compromises like I'm gating the clock to some of the 74LS374 which...

CPU operation
Log from One instruction VGA computer
I want to add a quick note for operation of the CPU.The CPU only does move instructions. So each instruction is a source address and a destination address. The memory map of the processor is simple:Address: Function0: Trash...

Brief Update...
Log from Blinkenrechner
I built my 2nd revision CPU (dubbed Zeta-2 because obviously it needs a badass name) and tested it's basic functionality. Manually operating the control lines, I was able to run each subsystem of the CPU and add, subtract, etc numbers. However, a number...

Looking at porting the 4 Bit CPU to a FPGA
Log from Hardware Controlled 4 bit CPU
A Virtual PCB At least that is how I explained it to my partner! It seems as if FPGA boards are pretty rare, almost all the main suppliers are out of stock, but I did find a Tang Nano 9k on ebay in Australia. So that is what I will use. Gowin (the FPGA...

G8PP+Z80, Part 4
Log from Generic 8-bit Processors Prototype (G8PP)
I like the idea of two separate boards, a common G8PP memory/IO/CF board, and a CPU board. I've designed 5 CPU boards with that concept in mind. These CPU boards have male RC2014 connector on one side and female RC2014 connector on the other...

Reading of 6502/65816 CPU Registers by a PC-based Debugger
Log from X65-SBC
Modern microcontrollers and microprocessors have built-in facilities for external debuggers to read/write registers, set breakpoints and generally fully control the CPU. This is one of the main usecases of the standard JTAG interface. The 6502 and 65816...

First successful run
Log from TMS9900 compatible CPU core in VHDL
After some debugging I got the TMS9900 CPU core to run on the FPGA chip. That's very cool! Even in this completely unoptimised form it runs a fair deal faster than the TMS99105 processor shield I built before. The CPU core is not yet fully functional,...

CPU-16 Final Design
Log from A 16-bit CPU in Logisim
First I'd like to thank people who have contacted me, liked, followed or asked to join the project. I'd like to everyone who has given me advice and helped me learn something new.After a hiatus, I have finalised the design for my 16-bit CPU. ...

Processor pin description
Log from 1 Square Inch TTL CPU
In this log I will explain more about the connections to the CPU. To use the processor, you only need the databus, address bus and control bus to connect memory and I/O to the CPU. PROG/ must be high (inactive) and EN/ must be low (active). Address lines...

Video and CPU sharing memory
Log from Big Daddy 68k
If the video display and CPU are to share the same RAM, then some way is needed for them to concurrently access it. The video data has to be written out to the screen on a fixed schedule as that pixel will be expected by the display at the correct instant....

Front Panel Operation
Log from PDP-8 FPGA
PCB arrived. Built it. Tested it. It took a lot of FPGA tweeks to get it working like I want. Pushbuttons DISP - cycles between DISP LEDs [AC, MD, MADR, PC]STEP - single step the CPULDPC - load the PC from the bottom slide switchesDEP - store the...

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