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3350 Results for "%E3%80%8A%EC%B5%9C%EC%A0%80%EA%B0%80 O1O%CE%9E5793%CE%9E7458%E3%80%8B %EA%B0%95%EB%82%A8%EC%95%84%EC%9D%B4%EB%A6%B0%EC%8B%9C%EC%8A%A4%ED%85%9C%E3%86%8B %EA%B0%95%EB%82%A8%EC%95%84%EC%9D%B4%EB%A6%B0%EC%85%94%EC%B8%A0%EB%A3%B8applause%EA%B0%95%EB%82%A8%EC%95%84%EC%9D%B4%EB%A6%B0%EC%8B%9C%EC%8A%A4%ED%85%9C%EA%B0%95%EB%82%A8%EC%95%84%EC%9D%B4%EB%A6%B0%EC%8B%9C%EC%8A%A4%ED%85%9C%EC%8B%A0%EC%82%AC%EC%95%84%EC%9D%B4%EB%A6%B0%EC%A3%BC%EB%8C%80caught %EA%B0%95%EB%82%A8%EC%95%84%EC%9D%B4%EB%A6%B0%E3%8F%87%E3%85%97%EA%B0%95%EB%82%A8%EC%95%84%EC%9D%B4%EB%A6%B0queer"

  • All Your ISA Belong to Me!

  • Before I began the layout of the DDL4-CPU, I came up with an initial Instruction Set Architecture (ISA) for the design. It went through several revisions as I was designing the boards and refined the components. Here at the last minute as I am...
  • 20230219c -- ROM test file

  • While whizzing through the code trying to scrounge verified keyboard scan codes and flags, I found some some buried treasure in the form of an undocumented test routine.  It's not that exciting -- it just fills the current file with some sample...
  • muahaha, I cheated :)

  • So since the Teensy++ 2.0 bootloader is not available and I'm not feeling comfortable to learn all the bells and whistles of USB communications I was looking for other options. Googling "at90usb1287 arduino" I found this https://github.com/mattairtech/ArduinoCore-avr...
  • OPS ENUMERATED - Draft

  • This represents a complete OPCODE list with 14 Constants (int values) available and 10 Labels (byte values) available for creating subroutines. Constants were favored over Labels, but this is up for evaluation. NOP and HCF were both added to the official...
  • Control Board FPGA Pinout

  • I might be missing a few connections yet which I'll correct as I come across them, but here is the pinout of the XC3S250E FPGA on the control board.  Note that the SRAM and the Flash share an interface bus.  Also note that the JTAG interface...
  • 20230213b -- Memory

  • I find it vexing that I have not yet figured out the RAM banking scheme.  Some things:at reset, the peripheral configuration registers and internal RAM are mapped at 0000h.  They can be moved elsewhere, but are not.  The RAM at 40-ff is...