Close

8965 Results for "8-bit cpu"

  • Adding 16 bit ISA support

  • Today I will be adding 4 project logs, 3 of which are a bit overdue.For the first, sometime back in June of last year, I began to look into the simple ISA implementation used to interface the Cirrus Logic CL-GD5429 SVGA chip to the 68332. My intention...
  • TD4B CPU Schematic and Simulating a TTA CPU

  • TD4 CPU Version B  Here id the full schematic And the PCB: Simulating A TTA A TTA is a Transport Triggered Architecture (i.e. a single instruction move only CPU). An example is my Weird CPU. Why simulate TTA? It is a good test for a CPU, can it...
  • Robby compiler for Voja's 4-bit processor?

  • Since new Supercon badge was introduced I started thinking about possible porting of my Robby compiler (aka nedoPC SDK) to this 4-bit processor - it should be doable. Robby is a programming language that operates only 16-bit signed integers. I can write...
  • PCB's ordered

  • Two PCB's are designed now:The CPUA mainboard for the CPUThe video part is not designed yet. The mainboard has a 96 pin connector (same as CPU) where the video PCB can be placed once it is ready.Here comes the CPU impression from the PCB makers website:And...
  • Jelly as a HRM

  • Today, I discover about "Human Resource Machine",  (https://tomorrowcorporation.com/humanresourcemachine) by  https://github.com/adumont/hrm-cpu, https://github.com/nrkn/hrm-cpu and https://spectrum.ieee.org/three-computer-games-that-make-assembly-language-fun.The...
  • CPU Board

  • Last but not least, the CPU Board that holds the MC14500 ICU, together with a 8-Bit Input and 8-Bit Output IC. Instead of the MC14599 Input / Output chip, I use the MC14099BCP instead - or it's still available equivalent, the CD4099B, that is still sold...
  • 16-bit Instructions

  • The redesign continued to ECU section. The changes are fairly significant, so much so that the breadboard build needs to start over. It was almost back to the drawing board, but the CPU section remains fairly intact. The result is another reduction in...
  • State Machine and instruction types

  • When I was coming up with new Register Transfer Scheme,  and in general while rethinking the design approach for this CPU, I realised that the explicit state machine will be the way to go. At the time I thought it would consist of quite a few of...
  • A Demonstration Program for a One Bit CPU

  • A Demonstration Program for a One Bit CPU I was thinking about a suitable demonstration program for a one bit CPU. My design has 4 inputs, two memory bits and 5 outputs. Long time ago a friend had three 4PDT switches and two LEDs wired up to count the...
  • MISC Core Already Sports 8 Instructions

  • NOP, LIT8, LIT16, LIT32, SBM, SHM, SWM, and SDM are implemented.NOP is the no-operation opcode, of course.LITx loads an x-bit literal onto the data stack.SxM stores a byte, half-word, word, for double-word value to memory.In a mere five hours of hacking,...