FPGA Blinker

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A while ago I needed a quick and dirty way to see what's going on in a clocked down design of mine and found myself with no appropriate tools around (and I was like "oh, shift / carp, digging into something as simple as this with an MSO / logic analyzer is an overkill"). Few hours into it and the "blinker" was born.

The design is straightforward - row scanner (driving low side NMOS current sinks) and column current sources (FPGA I/O cells in this case). On each clock cycle one of the R_i lines is asserted, the corresponding NMOS transistor is switched on and starts sinking current to the ground, while the C0-C7 lines are wired to the byte to be displayed, or, like in ((logic cell)register_bit[j]→(I/O cell)C_j)→[220R]→LED(c_j⇥⎯r_i)→NMOS_sink_i→GND. The value of 220R was chosen so that the column wouldn't draw more that 5-6mA pulsed current from the FPGA I/O cell. The selected NMOS transistors are capable of handling 8x6mA safely, so this shouldn't be a problem. The general formula is R_limit = (Vcc - Vled - Vds_drop) / I_led. One may ignore the drop term for simplicity, it will lower the max current figure a li'l bit, but it's OK).

If you need more current / higher Vcc, you must use a high side driver as well, which usually is implemented with an NMOS-PMOS pair (or NPN-PMOS, but I'd rather stay away from logic + BJTs). PMOS transistors are inverse logic devices (logic 1 means off) so a second NMOS or NPN transistor is added, acting like an inverter. It also isolates the logic output should the high side driver is sourcing current at a voltage level higher than Vcc. You may want to read AN804 / Vishay Siliconix. The overall picture changes to (((logic cell)register_bit[j]→(I/O cell)C_j)→NMOS_inverter_j→(Vcc→PMOS_source_j))→[RRR]→LED(c_j⇥⎯r_i)→NMOS_sink_i→GND.

While you may skip the bypass caps (step 4, 2x100n, 2x10u) if you go low side only (stop at step 10), having both drivers requires a "good" bypassing (as good as it gets on a protoboard), you'll be pulsing the Vcc rail after all.

Follow the building steps. Once your board is ready, test it. Connect the Vcc/GND to a 3.3V PSU (or a 3V battery pack). Nothing should be lit, there should be no current flowing (use a DVM set to a mA range). Now connect all of  the columns C to Vcc, the matrix should still be dark, no current. Proceed by asserting the individual R lines and you should see a lit row of LEDs (less than 50-60mA on the meter). This pretty much ensures there're no shorts / blown FETs / bad solder joints etc. This test is also good for the C' pins.

You're now ready to connect your blinker to the EB85. Go for the I/O pins of the J4 header (it also has 3.3V pins on it and is close to the edge of the EB). Use jumper wires and connect the GND, R0-R7 and C0-C7 / GND, Vcc, R0-R7 and C'0-C'7 (but never both C and C' pins at the same time, if you also soldered the high side driver). Don't use the J3 pin (pin 22) as it's connected to the 12MHz oscillator.

Now go to and download iCEcube2 and Diamond Programmer. Set the jumpers on your EB85 so that you'll be programming the CRAM over USB (or the serial flash if you want). Fire the iCEcube, create a new project and copy-paste the Verilog code (matrixdriver.v. You'll have to define a PCF with CLK input set to J3 and rows[0]...rows[7] and columns[0]...columns[7] set to the I/O pins you have just chosen. Consult with the iCEcube manual. If everything is OK you'll see the 64bit LFSR pattern from the Xilinx XAPP052 flashing, shifting right every ~90ms (~11Hz). Enjoy!

My "blinker" in action:

Sure enough, you may also display hexadecimal numbers with this driver, you only have to upload a different Verilog design (segdriver.v) and connect the rx/cx pins in a slightly...

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RC driver design

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7seg driver design

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"DaveCAD(TM)" ( style schematic diagram, too simple to bother with a real CAD for it ;)

Adobe Portable Document Format - 294.18 kB - 09/07/2018 at 14:44



AN804 Vishay Siliconix

Adobe Portable Document Format - 73.99 kB - 09/08/2018 at 12:33



XAPP052 Copyright Ⓒ 1996 Xilinx, Inc. All rights reserved.

Adobe Portable Document Format - 479.33 kB - 09/08/2018 at 12:11


  • 1 × EB85 Lattice ICE40-HX8k breakout board, Mouser p/n 842-ICE40HX8K-B-EVN
  • 16 × BS170 small signal NMOS transistor, Mouser p/n 512-BS170
  • 3 × 100n ceramic capacitor, 50V
  • 3 × 10u tantalum capacitor, 16V
  • 6 × 2x10pin female socket e.g. Mouser p/n 710-61301021821

View all 12 components

  • 1
    Docs, docs, docs...

    Print the datasheets of the EB85 board, the TA15-11GWA LED matrix, the BS170 and BS250P transistors and the schematic diagram.

  • 2
    Preparation step

    Unpack the EB85 board and populate J1, J3 and J4 with the six 2x10 female headers. Sure enough, the standard ESD protection guidelines apply or you may end up with a dead I/O bank(s), or, even worse, dead logic cells. Put it back in its antistatic bag.

  • 3
    Soldering the passives

    Solder a veritical bus of pads on your protoboard (the length depends, use something like a 28-ish AWG tinned wire). This will be your GND and you'll be soldering the sources and the gate resistors of the low side NMOS drivers to it (check the schematic and the pics). Solder two of the 10pin female headers horizontally (let's label the pins from left to righ on both headers, the leftmost pin being pin 0; the left header will be referred as R(ow) and the right one as C(olumn)). It should look like (R0)(R1)(R2)(R3)(R4)(R5)(R6)(R7)(R8)(R9)(space)(space)(C0)(C1)(C2)(C3)(C4)(C5)(C6)(C7)(C8)(C9). Solder 8 220R column resistors between pins C0...C7 and adjacent pads on the protoboard.

View all 15 instructions

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