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V20-MBC: a V20 (8088 + 8080) CPU homebrew computer

An easy to build homemade single board computer with a V20HL aka uPD70108H (8088 + 8080) or 80C88 CPU. CP/M-80 and CP/M-86 supported.

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The V20-MBC is an easy to build V20HL (full static CMOS version) or 80C88 CPU SBC (Single Board Computer). It follows the same "concept" of the Z80-MBC2 (https://hackaday.io/project/159973), with an SD as "disk emulator" and up to 1024KB RAM.

It has an optional on board 16x GPIO expander, and uses common cheap add-on modules for the SD and the RTC options.

It has an "Arduino heart" using an Atmega32A as EEPROM and "universal" I/O emulator (so a "legacy" EPROM programmer is not needed) programmed with Arduino IDE.

It is compatible with the uTerm (https://hackaday.io/project/165325) and uCom (https://hackaday.io/project/165709) boards.

* * PREFACE * *

Luckily I have enough electronic stuff "to survive" these days, so I decided to start the design of a new "retro" board, this time using a V20HL CPU. Of course my way...


* * THE PROTOTYPE * *

In the first phase of the design I've used a prototype on a breadboard to check the basic "concepts".

To make things easier I've used as "companion" MCU a STM32F030R8 on a custom board (ARMando) I previously made and that it is directly pluggable on breadboards, and with onboard microSD card and USB-serial adapter.:

To make the firmware for the STM32F030R8 I've used Arduino IDE with the core made by ST. In this way the "porting" to the Atmega32 used in the final board would have been simpler.
Here some screenshots of some tests using the 8080 mode to run the Altair Basic and the IMSAI Basic:





* * HARDWARE OVERVIEW * *

Here the V20-MBC hardware main specs:

- V20HL full static CMOS CPU (uPD70108H)

- can be used an 80C88 (CMOS version) too;

- RAM can be configured as 128/512/1024KB;

- optional RTC and microSD modules (the same used in the Z80-MBC2);

- optional 16x GPIO port;

- I2C expansion port;

- serial port;

- User led and key:

- ISP connector (for the Atmega32);

- clock can be configured at 4/8MHz (by software).

The CPU is used in "minimum mode" to limit the BOM.

The layout allows to "plug in" a uTerm or a uCom board as in the Z80-MBC2 (vertically or horizontally) using the same 3D printed brackets (the following screenshot could change due to IOS updates).

The following two images show a V20-MBC attached to a uTerm board to form an "autonomous" unit with a PS/2 keyboard and a VGA monitor:

Because it is a "two flavors" board (8088/8080), I've used a two flavors ice cream as logo... ☺

(the following screenshot could change due to IOS updates)


Please remember that a CMOS full static CPU is required here, so the only V20 CPU that can be used is the V20HL (uPD7108H, see the "H" at the end of the part code that makes the difference...).

Only this CMOS full static version allows to use a clock rate from DC and, under some conditions, guaranties that the logic levels are compatible with the Atmega32A ones (the Atmega logic input levels are not TTL compliant)

Another aspect of the V20-MBC is that the well known 8284 clock oscillator chip (normally used to generate the 8088/8086 clock with the required 33% duty cycle) is not used here. Reading  the V20HL datasheet you can see that the -12 and -16 speed grades have a symmetrical clock requirement, and the -10 speed grade clock requirement can be met using a little lower clock with a 50% duty cycle (not greater than about 9MHz, so using a maximum 8MHz clock there is a good margin).

In the Files section you can find the V20HL Datasheet.


RAM CONFIGURATION

The V20-MBC allows three different RAM configurations:

  • 128KB (1x128KB)
  • 512KB (1x512KB)
  • 1024KB (2x512KB)

To set the proper RAM configuration two jumpers (JP1/A19 and JP2/A17) must be set. This operation must be done when the board is not powered, and before the first power on with the RAM chips installed.

Please note that using a 128KB SRAM only the single SRAM chip configuration is supported (the 2x128KB is not supported).

The following table shows how to set jumpers JP1 and JP2 for the three RAM configurations:


CONSIDERATIONS USING AN 80C88 CPU

The V20-MBC can use an 80C88 CMOS CPU too.

Of course when using an 80C88 CPU you loose the 8080 mode specific of the V20HL CPU.

Please consider that when using an 80C88 a speed grade -2 is required (80C88-2) to meet the 80C88 specifications. If we see at the datasheet the clock requirements are:

So a 8MHz clock with a 50% duty cycle will no meet both the 80C88 and 80C88-2 specifications, but a 4MHz clock with a 50% duty cycle will meet the 80C88-2 specs.

So you have to use an 80C88-2 CMOS CPU setting the clock at 4MHz.

Of course you can try to overclock...

Read more »

SD-S260320-R230520-v3.zip

The content of the microSD for IOS S260320-R230520. Added the /teratem folder with files and instructions to setup an 8088 assembler automated toolchain. See ChangeLog.txt inside the SD image.

Zip Archive - 2.63 MB - 06/19/2020 at 14:13

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S260320-R230520_IOS_V20-MBC.zip

The sketch for the IOS (with the needed libraries). Unzip into a folder and open the .ino file (with Arduino IDE). IOS must be uploaded into the Atmega32A flash. Added CP/M-86 support. See the Changelog in the .ino file. The Serial port speed is 115200 bps (8N1).

Zip Archive - 38.58 kB - 06/04/2020 at 17:53

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S260320_R230520.ino.with_bootloader_atmega32_16000000L.hex

The sketch for the IOS in executable format (.HEX) with the bootloader. This executable file is intended for use with a programmer as the Atmel Ice or AVRISPmkII or others (Fuse bits: High Byte 0xD6, Low Byte 0xAF, Lock Byte 0xCF)

x-hex - 57.84 kB - 06/04/2020 at 17:55

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CPM-86 Personal Basic 1.1 Tutorial.pdf

Tutorial and manual for DRI Personal Basic v1.1 for CP/M-86. Please read it before to start using Personal Basic for CP/M-86.

Adobe Portable Document Format - 2.79 MB - 06/04/2020 at 09:45

Preview
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A250220 - SCH.pdf

Schematic.

Adobe Portable Document Format - 221.90 kB - 04/21/2020 at 11:27

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View all 10 files

  • iLoad: How setup an 8088 cross-assembler automated toolchain (Windows)

    Just4Fun06/20/2020 at 10:17 0 comments

    I've added a new paragraph on how to setup an assembler (8088) automated toolchain under Windows using the iLoad boot mode.

    See the "ILOAD: HOW SETUP AN 8088 CROSS-ASSEMBLER AUTOMATED TOOLCHAIN (WINDOWS)" paragraph in the Details section.

  • CP/M-80 emulation under CP/M-86

    Just4Fun06/10/2020 at 16:49 0 comments

    I've released a new SD image that adds in the drive F: of the CP/M-86 Disk Set a CP/M-80 emulator under CP/M-86 using the V20 8080 mode (VCPM15.CMD).

    In this way it is also possible run Catchum or send/receive a file with XMODEM:

    For more info see the "EMULATING CP/M-80 UNDER CP/M-86" paragraph in the Details section.

  • CP/M-86 is out!

    Just4Fun06/04/2020 at 17:59 0 comments

    CP/M-86 is out!

    Remember to update both the IOS firmware and the SD image (see Files section):


  • Testing CP/M-86...

    Just4Fun06/02/2020 at 17:04 0 comments

    Currently testing CP/M-86:

    The custom Bios sizes the installed RAM (128/512/1024KB) and changes the CP/M-86 available TPA accordingly.

    Here Turbo Pascal for CP/M-86 and Wordstar 3.3 for CP/M-86:

  • New IOS with CP/M 2.2 (8080 mode) is out!

    Just4Fun05/20/2020 at 17:08 0 comments

    The new IOS with CP/M 2.2 (8080) is out in the Files section:

    Remember to update the SD image too!

    The Details section will be updated with new info ASAP...

  • Testing CP/M 2.2 (8080 mode)...

    Just4Fun05/18/2020 at 12:00 0 comments

    I'm currently testing CP/M 2.2 using the 8080 mode:

    Of course only the CP/M applications strictly using 8080 machine code can be used here.

View all 6 project logs

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Discussions

freefuel wrote 3 days ago point

allow me to apply some arm twisting, if we ask very nicely can we have an ISA card version of this for use in a passive backplain? 

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Ken Yap wrote 2 days ago point

I doubt it because it would be a total redesign to bring out the buses to fingers, add transceivers, and all that guff. Return that ISA bus to the museum you took it from. 😉

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RW wrote 06/06/2020 at 13:15 point

You seem to be saying a 80C88 -2 is needed for 4Mhz, when I do the math, reciprocal of double the minimum low time for 50% cycle... I get ~7.3 Mhz for the -2 and ~4.2Mhz for the plain Jane. Still processing the deets, but not sure how it needs 70ns RAM either, since 120 should be good over 8Mhz, or is the ATmega writing to it faste?

  Are you sure? yes | no

Just4Fun wrote 06/06/2020 at 13:52 point

I've added 10ns for the rise and fall time, so the minimum period (50% duty cycle) for the 80C88 is (118ns + 10ns)*2 -> 3.9MHz.

About the RAM speed grade the 70ns is only that one I've used because it is cheap and  easy to find on ebay... A 120ns one should be fine as far as I remember (yes... the phrase I've written can be misleading in this case...)

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RW wrote 06/06/2020 at 14:37 point

Ah right, thanks. Guess even if you condition it with fastest through hole logic it's still 5ns. However, I'll assume the engineers left themselves 5% wiggle room and 99% of the "-1" parts will work. I'll have to try deciphering the date code on mine (Harris) and if it's not in the first few months of production, it should be good. If it isn't, give it another .5V and try again LOL. Particularly as Harris seem to have super good processes (They put out 25Mhz 286s etc). I think I saw a simple way to fiddle the duty cycle also, will look into that. 

Edit: Hey wow, an edit button. So checked out mine, seems to be 3 years into production, so I would hope they got them well tuned by then. Oddly though, there's a slight scuff on the package where they'd put the -2 or -10 -12 etc, and the scrap industrial control board it's sitting on has a 12Mhz crystal, all the other parts seem fast enough for 12Mhz too. So I don't know if it is a "-1" and that clock is divided in 3 or 4, or it's clocked at 6 with some duty cycle modification, or whether it was deliberately scraped off because they put a -10 on a 12Mhz board. Was made in 1986, so I think there was a huge enough price difference between speed grades then still that A) They wouldn't use 12Mhz capable parts on a board that ran half that speed B) they might have tried to save $20 on the 10 instead of 12.

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villaromba wrote 06/05/2020 at 16:02 point

CP/M 86  = Perfect !!! Thankyou.

BTW XMODEM fully working, for whatever reason SERIAL_RX_BUFFER_SIZE in HardwareSerial.h  had gone back to original values. When I looked at the .INO I realised IOS:

'Found extended serial Rx buffer' was not being shown ...... it all came back to me from SBC days....  it's an age thing!!!!

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Just4Fun wrote 06/06/2020 at 09:05 point

Great!

BTW: If you update the MightyCore library you will loose yours changes...

About XMODEM: I haven't found a XMODEM version for CP/M-86. If you found one let me know...

  Are you sure? yes | no

villaromba wrote 06/06/2020 at 12:09 point

Will seek !  

http://www.eolith.co.uk/mirrors/cpm86/files.htm  holds some interesting programs including Forth 83 which I transferred &  seems to work ok. Also some working File/Directory utilities  e.g  nsweep.cmd, sd.cmd. Much for specific IBM pc but will look through some of the others programs. Documentation good.

  Are you sure? yes | no

Scott wrote 06/13/2020 at 03:29 point

I have recently been working with CP/M-86 (V1.1 for PC) using QEMU as a virtual (PC) machine (as a fork off from the V20MBC project). I was able to successfully interact with the VM via a serial port (AXI and AXO) set up to be a UNIX socket, which then used SOCAT to translate it to a virual serial port for PICOCOM, which used the external SX and RX programs under Linux. I too found there was no XMODEM-86 available for CP/M-86 nor is there a CP/M-86 KERMIT available for the IBM PC/XT machines. However, I found MODEM9 (MODEM 7 fork from CP/M-80), which does use XMODEM for U/L and D/L. It can be found here https://www.z80cpu.eu/mirrors/klaw/86comm.zip. I'm sure that it can be slightly modified to work on the V20MBC since all I/O is done through the CON: device. The CP/M-86 ASSIGN utility may be used to remap logical and physical device I/O as well.

Peace and blessings,

JQ

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Scott wrote 05/27/2020 at 07:18 point

Ordered PCB from eBay vendor out of TEXAS. It arrived today. Build was non-traumatic. 

I couldn't find the ATmega32 fuse settings anywhere in the project files. Might be helpful to add them to the IOS source code for reference. I ended up using lfuse:0xFF and hfuse:0xC6

All I have on hand is older 8088's from AMD (DC: 1978) and an INTEL. 

The V20 I have is D70108C-10, which is not the D70108H that was said to be required for this board. **However, the D70108C-10 works fine.**

Idle current is about 70ma. Active current peaks at just under 100ma.

XMODEM: running V20 at 8MHz was successful with U/D load of 1MB file.

Since the Z80MBC2 supported QP/M 2.71, I copied those disk images over to the SDcard but had to modify the IOS source code to allow 2 disk sets rather than just 1 as is current config and add the DEFINES from the Z80MBC2 source code. Weird because QP/M loaded the 1st time but it will not load any longer.

CP/M 3 and PASCAL would not load. I did not look into the reason(s) why. CP/M 3 is likely due to banking set TRUE.

Right now, the V20MBC is a glorified 8080. Any chance to get some 8088/8086 code running on it? CP/M-86 is available but seems very limited.

J4F - thanks again for another great "hybrid-retro" design. I love the "new" instruction stuffing method used since Z80MBC2.

Peace and blessings,

JQ

  Are you sure? yes | no

Just4Fun wrote 05/27/2020 at 09:40 point

Hi, thanks for the info. If you try to use the Z80-MBC2 CP/M, it contains a BIOS with Z80 specific code that doesn't work with the 8080 mode. The same is for CP/M Pascal. I haven't checked for QP/M.

About 8088/8086 specific code, I'm thinking about it...

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Scott wrote 05/27/2020 at 10:13 point

Hi: I figured the issue was Z80 code vs. 8080 code. I just hadn't gone looking through the code for those loaders yet.

It's odd that the QP/M loader brought up CP/M and I retrieved a directory listing of drive A:. Then it never worked again.  Maybe the V20 thought it was a Z80 for a moment then suddenly realized it was an 8080. :)

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Just4Fun wrote 05/27/2020 at 10:20 point

About QP/M, also its BIOS uses Z80 specific code (it is very close to the CP/M one).

  Are you sure? yes | no

Scott wrote 05/30/2020 at 20:21 point

Yes, the Z80-MBC2 loaders are all Z80 mnemonics.  I may take the time to modify at least the QPM files.

I know, there's not much code available for 8088/8086 single board computers. It's all DOS or PC BIOS related. Sigh... :)

With some effort, Dave's  MON-85 monitor may be modified to work with [s]8080[/s] 8088 code, which would be good since MON-85 allows one to set and use up to 8 software breakpoints.

Peace and blessings,

JQ

  Are you sure? yes | no

Just4Fun wrote 05/31/2020 at 09:22 point

MON85 for the V20-MBC is already available in the /8080 folder... (see the DETAILS section...)

  Are you sure? yes | no

Scott wrote 05/31/2020 at 19:07 point

Sorry, my prior post should have stated "8088", not "8080". :(

Yes, MON-85 for the V20 running in 8080 mode. I was talking about mods to bring it up to 8088 usage, so "MON-88". 

As I recall, there are translators for 8080 to 8086 mnemonics. Would be interesting to see MON-85 run as "native code" on the 8088. :)

Peace and blessings,

JQ

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villaromba wrote 05/23/2020 at 09:49 point

Just loaded the new revision with XMODEM  and replaced the SDCard files. When I run XMODEM it just hangs.... All OK or you ??

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Just4Fun wrote 05/23/2020 at 10:51 point

Tested now and it seems that it doesn't receive... strange because I've tested it a few days ago and worked in both directions... Hmmm...

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villaromba wrote 05/23/2020 at 11:15 point

Try @ 4Mhz, it works for me at lower rate....

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Just4Fun wrote 05/23/2020 at 11:12 point

it seems that only very little files can be received... strange because I've tested it with big files (500KB) in both ways without any problem... but not working now...

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Just4Fun wrote 05/23/2020 at 11:33 point

No differences for me @4 or 8MHZ. I can send and receive a 190 blocks file as MBASIC85.COM but if I try to receive a big file (about 500KB) it closes the receive session without receiving nothing. This is very strange as I've tested it without any problem with big files... and I haven't done any change...

  Are you sure? yes | no

villaromba wrote 05/23/2020 at 11:44 point

Just dumped a 1200Kb .txt file over (took 6.18mins) but went over without a problem.

BTW I'm running an ATMega32, In theory I think it should be ok  but I will burn a Mega32A just in case !!! 

OK: With Mega32A no difference, nothing at 8Mhz  all good at 4Mhz

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Just4Fun wrote 05/23/2020 at 12:00 point

So @8MHz you can't transfer any file (little or big) and @4MHz every file (little and big) without any problem?

  Are you sure? yes | no

villaromba wrote 05/23/2020 at 12:06 point

@8MZ a  5Kb file hangs at 2.7% xfer. Everything seems to work @ 4Mhz. Just xfrerred Zork 1, 2 & 3 over too without any problems

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villaromba wrote 05/23/2020 at 12:20 point

ok A little more info e.g with XMODEM ZORK1.DAT /S,  a send - works @8 & @4 Mhz just the /R that seems to be the problem at 8Mhz

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Just4Fun wrote 05/23/2020 at 12:16 point

WAIT!!!! All previous (my) problems are fake!!!!

I was using a corrupted (big) test file inside my VM!!! (OMG!!!)

Now it is all working @4 and 8MHz with every kind of file (little and big) in both ways... (as during my previous tests).

So no little bad ghost inside my V20... :-)

  Are you sure? yes | no

villaromba wrote 05/23/2020 at 12:23 point

Well that's good news (I think!!!) - I can live with  Xmodem @ 4Mzzzz it's not used that much any rate. Next week I should complete my 2nd build. Be interesting to see how that does.

BTW Thanks for all the  tests and updates......

  Are you sure? yes | no

villaromba wrote 05/21/2020 at 15:45 point

CP/M loaded up fine and running well. Without PCGET and or Xmodem I've got to revise my cpmtools GUI usage !!

On my 2nd board I am going to fit 2 x 40pin ZIFs, may need some re-positioning. I bought a little while ago 8x M80C88A so will try them out. The other ZIF for the ATMega for ease of programming it. Yes, I still use the TL866 !!!

  Are you sure? yes | no

Just4Fun wrote 05/21/2020 at 16:01 point

The XMODEM used in the Z80-MBC2 uses Z80 machine code as far I remember. If you know an 8080 working version let me know...

BTW I don't know PCGET. It can be used on 8080 CPU?

ABOUT CPMtoolGUI: You can use the format settings for CP/M 2.2 on the Z80-MBC2 (one for disk 0, the other for disks 1-15).

EDIT: It seems that I've learned a new thing today :-)

Just found this:

https://github.com/glitchwrks/pcget_pcput

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Just4Fun wrote 05/21/2020 at 17:06 point

BTW: I was wrong... The XMODEM used (and adapted by me) for the Z80-MBC2 uses 8080 assembler mnemonics... :-)

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villaromba wrote 05/21/2020 at 17:56 point

Thank you .... sounds good to me. I will do some 'experiments' over the weekend.

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Just4Fun wrote 05/07/2020 at 17:21 point

Just joined the #TechAtHome contest!  ( https://twitter.com/Just4Fun_J4Fun/status/1258440867477704704?s=20 )

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villaromba wrote 05/06/2020 at 16:45 point

Completed my build day today with the V20 and all seems to be working perfectly. Will let it run  a  basic prog overnight and do further tests with Forth  etc. tomorrow. BTW the Z8 also working great as well. Happy days!!! Thanks again for a further 2 boards. 

  Are you sure? yes | no

Just4Fun wrote 05/06/2020 at 17:01 point

Great!

Let me know...

  Are you sure? yes | no

villaromba wrote 05/07/2020 at 11:12 point

V20 still churning out data from the Basic8k78  this a.m. Checked out all the  .hex files in the 2 basics and forth. All working great. Running with 512k memory. My RTC should arrive tomorrow to complete the build. Probably won't add the expander IC as not necessary for me on this build. All MENU functions are good. 

I shall continue to 'watch this space' !!

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Just4Fun wrote 05/09/2020 at 09:34 point

When testing the RTC remember to apply the patch...

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Dave's Dev Lab wrote 04/22/2020 at 15:12 point

lovely build! i was looking at doing something with the V40!

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Ken Yap wrote 04/22/2020 at 12:36 point

It's a pity I cannot use the V20 chips in my spares box as they are not static although I understand the reason for that in your design, and previous ones. Anyway nice work.

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MS-BOSS wrote 05/01/2020 at 18:29 point

That's not entirely correct. You could design the board in such a way that when entering "idle" or "single-step" mode, the processor would execute until next instruction after requesting it to pause. Then, by decoding the memory access IO, you could detect it is going to load next instruction and supply it either with the WAIT instruction or the HLT instruction. Both are single-byte so it should be quite straight-forward.
WAIT instruction serves usually for communication with 8087, however it can probably be misused to pause the processor and then unpause it by its BUSY# signal. I am not sure, however, if that works in minimal mode (8087 was meant to be connected only in maximum mode). It seems this method may be broken by any interrupt that gets triggered when the processor is waiting.
HLT instruction should pause the processor until any event happens - debug session or interrupt. This may be broken by interrupt, again.
There may be another method which involves abusing the LOCK# signal to fool the processor into thinking it is runing in dual-processor computer which makes it wait until the second (fictitious) processor releases the bus. However, that probably won't work in minimal mode.
A last method which comes to mind is to use the RQ/GT pins to request/grant access to bus which should also pause the processor (I hope so).
As always, remember that even the lowly 8088 may start to behave funny since it has 6-byte FIFO for parsing instructions. This means that if you pause the processor, read the RAM, inject some code into RAM which would allow you to probe the context of the processor and then expect it to run properly - no way. It still has several instructions stuck inside which are going to be executed after you unpause the processor (it could jump out to some other part of code). A proper solution would be to stuff the processor (no matter what part of memory it tries to access) with some safe instructions (JMP $, HLT, WAIT, NOP, ...), then unpause it, let it crunch the safe instructions, pause again, then send your code to RAM and unpause again. OTOH, maybe an interrupt/jump/branch flushes the cache?

  Are you sure? yes | no

Ken Yap wrote 05/01/2020 at 22:30 point

Can it be done with the current board design?

  Are you sure? yes | no

Just4Fun wrote 05/02/2020 at 09:25 point

There is another constraint to be kept... Only the CMOS versions under "light" load conditions (see datasheet) have logic levels compatible with the Atmega ones (the Atmega are not strictly TTL compliant).
So no CMOS CPU no party (at least with the Atmega).

BTW: the STM32F030R8 I used for the breadboarded prototype has TTL levels, so it could work with non-CMOS CPU too, but the requirement here was to use THP only...

  Are you sure? yes | no

villaromba wrote 04/17/2020 at 19:24 point

My boards are being fabbed at JLCPCB - most parts waiting to go in !!

  Are you sure? yes | no

Peabody1929 wrote 04/12/2020 at 18:21 point

Can't wait to build one!

  Are you sure? yes | no

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