Since this computer uses a CPU that is about 45 years old, it cannot compete at all with today's computers in terms of performance. However, I wanted the PERSEUS-8 to have functions and appearance that would remind us of concepts that today's computers has lost. Figure 1 shows the appearance of PERSEUS-8.
Fig.1 Appearance of PERSEUS-8
The enclosure of the PERSEUS-8 is assembled cut out of aluminum materials. I used 2mm thick aluminum sheets and 15mm and 10mm aluminum angles. Only the bottom plate is made of 1mm thick aluminum. M3 screws and nuts were used to fix each part. This method is quite tedious, but it allows me to design my own free will. The outside dimensions without handles and rubber legs are WHD: 300 x 88 x 310 mm. The front panel was sandpapered for a hairline finish, and the side and top panels were painted with gray lacquer spray. Figure 2 shows the enclosure components before assembly.
Fig.2 Enclosure components of PERSEUS-8 before assembling
The following video shows the assembly of the enclosure.
3. Hardware configuration
Figure 3 shows the hardware block diagram and Fig.4 shows the main board of PERSEUS-8. When the CPU is set to the halt state by the front panel switch, the memory address and data can be set with Direct Memory Access (DMA) by the toggle switches on the front panel for programming. In this state, single-step operation is possible. The single-step control circuit performs these controls. The schematics PERSEUS-8_schematics_01.pdf are on the attached files.
Fig.4 Main board of PERSEUS-8
The CPU is the R6502A, the same as the PERSEUS-7, but driven at the highest clock speed of 2MHz.
The memory devices are two 64 k bit SRAMs (HM6264BLSP-10L). The total memory capacity is 16 k bytes. Of these, 8 k bytes were mapped to the zero page area side and 8 k bytes to the vector area side. The SRAMs were backed up by a 3.6V, 70mAh Ni-MH battery, the same method used in the PERSEUS-3. The supply current of the memory IC in the backup state is only 0.56 µA. It has a proven track record of retaining memory contents stably for 10 years. The memory protection switch was installed on the front panel this time, as it was difficult to use on the main board of PERSEUS-3. For the ROM, four 16kbit type 2716 PROMs that can be programmed with a homemade PROM programmer can be mounted. The ROMs can be selected between the RAM on the vector space side by a switch on the main board.
6. Panel switches and LEDs
Figure 5 shows the front panel switches and LEDs.
Fig. 5 Panel switches and LEDs of PERSEUS-8
Sixteen address switches are connected to address bus though 3-state buffers (74HC244). Eight data switches are also connected to data bus though 3-state buffers (74HC244). The address LED displays the execution address of the CPU, not the address set by the DMA. This is almost the same circuit as PERSEUS-7 except for the address bus width. In the serial interface, there are LEDs on the transmit/receive signals so that you can directly recognize the communication status.
7. Single step execution
Figure 6 shows the single step control circuit and Fig.7 shows the corresponding timing chart. The single-step circuit was designed to be as simple as possible by referring to the references ,. In R6502, there is no halt signal, but since the CPU sends out a SYNC signal in the first machine cycle M1 of each instruction, this can be used to disable the RDY signal given to the CPU to create a single step execution. The following is a description of how it works.
Figure 7 is the case of a single-step operation of an instruction that takes two clock cycles to complete the shortest machine cycles. The timing values in Fig.7 are based...Read more »