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Arduino Compatible Zynq Shield

Xilinx Zynq SoC, Arduino Compatible, 2x ARM Cortex A9, LPDDR2 Memory, USB OTG, on-board USB JTAG and UART.

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Lowest Cost Linux Ready solution to use the latest and greatest FPGAs ever made, Xilinx 7 series. Use as FPGA development platform, or run Linux on the Cortex A9 cores.

This was my first Zynq Design with LPDDR2 memory, and served as test for the DIPFORTy2 #Soft Propeller upgrade to include USB, HDMI and LDDR2 memory.

System Design

PCB tech: 8 layers no buried or stacked vias. Micron 64MByte LPDDR2 memory, this memory type needs no special termination and is housed in nice small package as well and should save some power as well.

Licenses

  • 1 × FT2232H Multifunction USB IC from FTDIchip
  • 1 × XC7Z010 Logic ICs / Programmable Logic: FPGA
  • 3 × EN5311 Power Management ICs / Switching Regulators and Controllers
  • 1 × USB3320 Interface and IO ICs / Subscriber Line (ADSL, DSL, HDSL, VDSL, SLIC)
  • 2 × SiT8008 MEMS Oscillator 52MHz and 12MHz
  • 1 × TPS2051 Interface and IO ICs / Peripheral Drivers and Actuators
  • 1 × S25FL127SABMFV10 Memory ICs / FLASH Memory
  • 1 × 93AA56BT Memory ICs / EEPROMs
  • 1 × LPDDR2 LPDDR memory from Micron
  • 1 × micro USB AB Connector micro USB AB Connector

View all 12 components

  • LED blink without CPU

    antti.lukats02/04/2016 at 18:39 0 comments

    For simple LED blink, we can use internal clock and forget totally that there is a hard processor available. This design work equally well on any Artix, Kintex, Virtex or Zynq board!

    If we want to write the Blinky in VHDL, then this is equally easy:

    We send the clock to output port, and create wrapper that is not managed, then we can just write normal VHDL. Of course we could just instantiate the startup directly in VHDL too.

    library IEEE;
    
    use IEEE.STD_LOGIC_1164.ALL;
    
    library UNISIM;
    
    use UNISIM.VCOMPONENTS.ALL;
    
    entity blink_top_wrapper is
    
      port (
    
        LED : out std_logic
    
      );
    
    end blink_top_wrapper;
    
    architecture STRUCTURE of blink_top_wrapper is
    
      component blink_top is
    
      port (
    
        clk66mhz : out STD_LOGIC
    
      );
    
      end component blink_top;
    
    signal clk: std_logic;  
    
    begin
    
    blink_top_i: component blink_top
    
         port map (
    
          clk66mhz => clk -- this is free running clock from BD
    
        );
    
        -- LED is steady on!
    
        LED <= '1';
    
    end STRUCTURE;

    This is basically the vivado generated wrapper, 3 lines changed.

    This design takes the clock from PS PLL, from FCLK0. This design only works if Zynq CPU has executed the FSBL (first stage bootloader). Again we can use this clock from the PS PLL in our plain VHDL code.

  • Production in progress

    antti.lukats09/11/2015 at 07:30 0 comments

    All PCB from first PCB batch are being assembled, availability announced soon.

  • Parallax Propeller 1 emulation in FPGA

    antti.lukats08/19/2015 at 18:24 0 comments

      IT is working now

      Zyn PS Block is only supplying clock into FPGA not used otherwise, all the work is done by the Propeller Soft Core implemented in FPGA Fabric.

      Prop P31, P30 are connected to FTDI USB UART, P0..P15 to Arduino D0..D15

      binaries on github, but need to FLASH them, they would not work if loaded from SD Card.

      HOWTO

      1. get the BOOT.BIN from github
      2. Write to flash, reset or replug usb
      3. start Parallax Propeller tool
      4. Press F7

      Should identify Propeller version 1

  • Flashing for linux boot

    antti.lukats08/18/2015 at 21:28 0 comments

    https://github.com/AnttiLukats/HackaZynq/tree/master/THP2015/pre-built

    there are BOOT.BIN and image.ub

    call C:\\Xilinx\\SDK\\2015.2\\.\\bin\\zynq_flash.bat -f BOOT.bin -flash_type qspi_single

    this will update the Flash with BOOT.BIN

    note: BOOT.BIN includes: FSBL (first stage bootloader, FPGA bitstream and u-boot)

    From flash only FSBL is loaded, then this FSBL loads from BOOT.BIN on SD Card

    FPGA bitstream

    u-boot

    executes u-boot,

    after that u-boot would load linux image from image.ub

    note: it is possible that terminal does not accpept input, please close and open putty, this should help, there seems to be a issue that some terminal program go nuts if the say some garbage during FPGA config. We are working on this..

  • files to github

    antti.lukats08/17/2015 at 18:56 0 comments

    full hardware design, CAD sources and generated files too

    https://github.com/AnttiLukats/HackaZynq

  • Linux 3.19

    antti.lukats08/14/2015 at 15:30 0 comments

    boot OK, the memory size is visible: 64MByte

  • Vivado Board Awareness

    antti.lukats08/10/2015 at 14:21 0 comments

    Two days of frustration, it seems that Vivado 2015.2 has an BUG related to PS presets and Board Part flow, as soon the system has been configured with LPDDR2 then the board files and presets become invalid. So we have fail a WebCase by Xilinx for this.

    It is not a shows stopper, it is possible to provide the presets and board files with LPDDR2 not enabled, and then later apply the required setting per hand.

  • 16 Channel Frequency Counter

    antti.lukats08/02/2015 at 12:03 0 comments

    16 Channel Frequency counter, the easy way:

    Step 0:

    Start Vivado, Create project, Create new Block Design.

    Step 1:

    Type freq.. and let the drop down to populate, then select the IP Core to be added:

    Press Enter!

    Step 2:

    Doubleclick and set number of channels to 16

    Press Enter!

    Step 3:

    Add AXI Register Bank, the Block diagram should look like this:

    Step 3:

    Click on the "Run Connection Automation! Click on OK!

    Step 4:

    Connect Frequency meter outputs to the register inputs, then connect the ref clock to Fabric Clock output from PS7 Processing Block, and make the Frequency meter inputs external, this is all done by a few mouse-clicks.

    Step 5:

    The Hardware is now ready for build, before final bitstream generation we would need to assign the DIN[..] pins to actual pins in the Arduino headers. After that we can close Vivado and continue with Software.

    Step 6:

    For quick test without Software, Vivado labtools VIO can be used:

    Frequency meter in action, D2 in Arduino header was connected to test clock with 33MHz


    This Frequency meter was used on the "zynq arduino" board during proof of concept testing of LiLi (Light Link) where a DDS was usd to generated the LED blink rate and the "frequency meter" IP Core did display the Frequency..

    This is Free IP Core, and if not yet published soon will be. It is fully ready for Vivado IP Core repository.

  • Cost optimization, run 1

    antti.lukats08/01/2015 at 10:17 0 comments

    PCB Rev 1 are working and usable but there is room for BOM cost optimization. Current sale price could be 89 EUR, with extensive BOM optimization it could be lowered - hopefully.

    USB micro-B to USB mini change

    FTDI USB connector is currently micro-B footprint (was actually mounted with micro-AB what is no go for real production). For some reason micro USB connectors cost much more than mini USB connector. As example chepest mini-USB connector at Mouser costs 0.145 EUR. Micro USB is currently in BOM with cost closer to 1 EUR!

    This change requires moving the connector components to make more room, but it is still doable and fits the PCB edge area available.

    OP Change

    The SOT23-6 packaged Operational Amplifier used for Analog input buffer for the Arduino Analog header inputs was chosen from our standard library, and is priced over 1 EUR. Footprint compatible part from Microchip costs 0.17 EUR only at Mouser. This is BOM change only no PCB change required.

    Reset Diode Change

    In the reset input we accidentially used almost first diode from our library it happened to be shottky diode in 0201 package, and not the cheapest one. This 0201 Diode is not so loved by SMD assembly operators as it is almost impossible to recognize the polarity marking as the Diode is bare die type, at the top the bare Si die is visible. This change required PCB change as well, PCB space is availabe no issues. Some BOM cost reduction will also come. Lowest cost diode at Mouser is about 0.032 EUR only. The 0201 Shottly Diode does cost much more.

    VCC Switch Diode Change

    There are 2 diodes in the schematic that are used to separate the power supplies, both list with 0.6 EUR in the BOM, quick search at Mouser shows suitable diodes priced 0.15 EUR.

    USB Power Switch

    TI power switch is listed with price over 1 EUR, quick search by Mouser shows SOT23-5 packaged USB Power switch pricing at about 0.35 EUR.

    PCB Price and technology

    PCB Rev 1 was made at prototype Factory so the PCB price for production can be lowered, but possible there may need to adjust the PCB technology and talk to the PCB fab about the pricing. Current PCB is 8 layer with small track and space rules and small vias. This will still most likely be the technology for production volumes as well.

  • LPDDR2 Working too!

    antti.lukats07/30/2015 at 20:29 0 comments

    First time ever my first board with LPDDR2, well as boring as usual, just working!

    LPDDR2 chip is on the the bottom side, really there :)

View all 14 project logs

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Discussions

EngineerAllen wrote 02/01/2017 at 22:56 point

you designed your own computer!

very impressive

the system design diagram isnt funny though..

how much does it cost for 1 or 2 units

even if i want to modify and get someone to fabricate + populate PCB?

  Are you sure? yes | no

miguel miranda wrote 02/10/2016 at 05:13 point

Hi, sounds great!!
you should take a look for the snickerdoodle board from krtkl maybe you can get some good ideas

  Are you sure? yes | no

diljith.m wrote 02/02/2016 at 15:15 point

Hi,

Cool board. Just received two of them from trenz.

Wonder where you are sourcing LPDDR2 chips from. I could not find a x16 chip when we wanted to use them recently.

  Are you sure? yes | no

antti.lukats wrote 02/04/2016 at 18:28 point

They are no longer available, this was bad news to us too. Micron had some, but then the stock vanished. They can still be sourced but minimum order is 20K. Per month unfortunatly :(

We had parts and promises from vendor that we can continue buying them. It was a lie unfortunatly. The distributor sold last stock, and that was it.

  Are you sure? yes | no

Yann Guidon / YGDES wrote 02/04/2016 at 23:34 point

that's why I don't commit to a design until I have all the parts in stock...

  Are you sure? yes | no

Dvorak Viktor wrote 01/26/2016 at 12:51 point

Hi, now the boards are available by Trenz. I have two boards and start experimenting.

Viktor

  Are you sure? yes | no

ben biles wrote 09/17/2015 at 12:29 point

HI, will this board work with the arduino due? can I use Xilinx IDE , the free one or Vivardo with the board ? does it have on baord JTAG if not can I hook any JTAG debugger up to it ? sorry I'm totally new to FPGA but am thinking the zinq7000 soc has more use for me than the Sparten6 since I want to have I2S IO and DSP complex multichannel audio mixing / routing.

Also, since the Zinq7000 series has dual core arm on board the fpga can this board be used stand alone ? I have a use for it conected to an arduino, mainly since my project could send controls over SPI or I2C to the FPGA but wondered if later I could run the board stand alone!!

thats if I learn how to code in the ARM cpu's..

sorry for the beginner questions, if the answer is yes to most of the above then i'd love to know the price and where to order ?

looks like a very powerful board !

thanks, ben

  Are you sure? yes | no

antti.lukats wrote 09/17/2015 at 12:52 point

Hi I am at IOTcongess in Barcelona, I did give one prop to Xilinx at their booth, they well will see..

Ok technical answers: we preflash with dual boot code that runs the propeller opensource version if no SD card is inserted or runs ARM CPU0 code from SD card if detected.

You can use the board as:

FPGA board with Artix - no use of the ARM core

As ARM board using default "GPIO" bypass FPGA design

as Soft-Propeller in 100% compatible mode

as Soft-Propeller with extensions + ARM cores

as ARM Cortex A9 with custom peripherals

--

partially ported arduino compatibility libs are availabel, they are made as Xilinx SDK libraries.

sorry, this is better to explain in separate posting.

you can use the module as standalone, or as addition to existing system (arduino, RPi) without any extra hardware needs

for JTAG debug, or FPGA debug an USB jtag adapter is needed. but this is not requirement for development, you can just build images that boot from microSD anc reconfigure fPGA and run custom code on A9 cores.

from wifi-cade in barcelone.. holaaa

  Are you sure? yes | no

ben biles wrote 09/17/2015 at 14:22 point

wow, thanks for reply, I have no FPGA experience, so I'll have to google up half of your reply , Artix ? is that xilinx IDE? Soft-Propeller ? sounds like a linux ! :)

not sure I understand why I need ported arduino Libs? can't I just run arduino code in arduino and communicate to FPGA over GPIO pins as I2C or SPI ?

booting ARM custom bare metal code sounds way out of my depth.. maybe if I booted linux on the ARM Cortex A9 and made peripherals..

phew..

I was hoping to use opensource IP modules to get I2S IO and audio processing hapening.. but no idea where to start..

let me know later which way I should go.. or if you think I can make use of this board. ! 

night time here in Japan !! have a fun day !!

  Are you sure? yes | no

liubenyuan wrote 08/29/2015 at 02:18 point

Hi, great project !

It would be nice if it would have an Ethernet port !!

  Are you sure? yes | no

antti.lukats wrote 08/29/2015 at 09:29 point

1) you can do ethernet over USB, with the usb gadget thing, works pretty well. Adding a RJ45 would have made it all much more bulky, etc. 

2) There is also some project that does wired ethernet 10mbit with FPGA pins - this is not so recommended

3) RMII ETH phy requires 7 I/O pins so could be even on shield addon

  Are you sure? yes | no

Adam Vadala-Roth wrote 08/17/2015 at 05:31 point

when/where can I get one

  Are you sure? yes | no

antti.lukats wrote 08/17/2015 at 05:33 point

We will assemble the remaining PCB from first batch next week I hope. So in max 2 weeks some boards are available. After cost optimized version will go in series production. At first we assembled on panel = 4 boards, 3 I sent to HaD so I only have one for testing at the moment.

The board will be manufactured by Trenz Electronic GmbH and will appear in the online shop soon too. But some units may be available before that time too.

  Are you sure? yes | no

Adam Vadala-Roth wrote 08/17/2015 at 05:40 point

Sounds great, maybe you should email hackaday and do a hackaday store version too!! that would be neat. 

  Are you sure? yes | no

antti.lukats wrote 08/17/2015 at 05:47 point

Ah with HaD logo and block solder mask? Yes this can be arranged.

  Are you sure? yes | no

hanxun1990 wrote 08/02/2015 at 15:34 point

where are the source files? Could I download them?

  Are you sure? yes | no

antti.lukats wrote 08/19/2015 at 07:04 point

check out the github link, hardware design files released under CERN OHL 1.2 Licesne

  Are you sure? yes | no

antti.lukats wrote 07/06/2015 at 13:38 point

Ah, yes :) well it is so complicated in legal terms not write something that would make the Arduino trademark owners angry. I have their legal stuff all over and over, and its complicated. But you are right, it is fully selfcontained board.

  Are you sure? yes | no

SUF wrote 07/06/2015 at 13:01 point

Hi,

Why this called "Shield"? It looks most like an independent dev board.

SUF

  Are you sure? yes | no

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