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Stanley Ng

Engineer doing RTL design/verification in FPGAs and ASICs

Bay Area, California
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stanley-ng
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This user joined on 05/25/2015.

Things I've Built

Prime Number Finder

Sieve of Erastothenes implemented in an FPGA. 2,010 counters each counting a prime modulus running in parallel to give "prime/no prime" indication for each clock cycle. No practical application but it's a neat demonstration for MakerFaire.

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Secure your Internet, control your data, fight censorship. Bring your autonomous all in one privacy device everywhere.
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Web security everywhere

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Follow for the 'Hacklet' and latest news about hackaday.io
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Hackaday.io Project

lutetiumLutetium

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Cornell ECE 5760 teaches FPGA design for DSP, video, and embedded control. Emphasis on parallel computing.
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Teaching FPGA parallel computing

bruce-landBruce Land

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Data Acquisition GUI in Matlab using ADC/DAC. Simulated instruments with REAL voltage in/out, with winsound or NIDAQ
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REAL voltage in/out with simulated instruments

bruce-landBruce Land

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Eagle files used to convert SMT chips to DIP format for use in breadboard prototyping.
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SMT to DIP Breakout Boards

kevin-neubauerKevin Neubauer

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A Mini cookie oven for your desk
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MicrOven

chazChaz

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