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FPGATED

Reimplement the TED chip of Commodore 264 series in FPGA

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A cycle exact FPGA core for the MOS 7360/8360 TED chip written in verilog.
The final goal is to have an fpga core that could be used as a drop in replacement for the MOS 8360 chip which is the heart of the Commodore 264 series 8 bit computers, namely the Commodore 16, Commodore Plus 4 and Commodore 116. This core can be the basis of a complete C16 or Plus 4 SoC implementation.

The idea of the project came when my 30 years old Commodore Plus 4 has suddenly died and I suspected that TED was the main cause. After an extensive troubleshooting it turned to be that the 8551 ACIA chip was the guilty one and I have fixed it, however by that time this project has been born in my head. I have checked the internet and was surprised that no one has created a TED FPGA core before.

Although there are some TED documents available on the internet, they are incomplete, not precise and do not fully describe the inner secrets of the chip. There is no point in creating a chip which is not cycle exact, doesn't emulate TED scan lines and events properly. An extensive research started on the hardware using own written test codes, logic analyzer, oscilloscope and source code analysis of Plus 4 emulators. I quickly realized that due to the inner multiplexed architecture of TED certain events are initiated at the specified time (described in 7360R0 preliminary data sheet) however they happen later in time after 1-2 single clock cycles. This behavior was emulated in certain emulators like Plus4emu, which made the emulator code much more difficult to understand.

Two years of analyzing the hardware, documents and code writing has led me to a working TED chip which is capable of running most of the programs and demos the same way as the original hardware. The project is not finished though, I am planning to refine it further and make it available to everyone.

The code is written in verilog language and uses Gadget Factory's Papilio One 500k developer board. This board has a Xilinx Spartan 3E 500k FPGA which is more than enough for implementing a whole Commodore computer except its main memory. The FPGA has only about 40Kbyte RAM which is not enough for a 64Kbyte computer especially if we think of the 16K Kernal and Basic ROMs. The TED core module doesn't use any Xilinx specific HW blocks or macros so it is very easy to reuse on other Vendor's FPGAs. Later on I have continued the development on the more advanced Papilio Pro board with Spartan6A FPGA and onboard sdram. Although I wanted to implement the TED chip , it was clear that I need to implement other supporting components (CPU, ROM, keyboard matrix) to test the chip on the FPGA board. As several 6502 CPU FPGA codes exists I did not want to reinvent the wheel and decided to use a publicly available one which has illegal opcode implementation also. I have chosen Peter Wendrich's 6502 vhdl code from the fpga64 project. Peter has confirmed via email that I can use the CPU part of his code for my FPGATED project and include its source in FPGATED sources.

Papilio TEDwing

First step of the project was to create the hardware developer environment, which means building a suitable wing board for the Papilio One FPGA board. Gadget Factory has already created an Arcade Megawing however it lacks the memory part which is crucial from the TED system's point of view. It was however a good starting point for the TEDwing design. These were the main design criteria for the Papilio TEDwing:

  • 12 bit VGA/RGBS output
  • 2x 4464 DRAMs
  • IEC serial bus connector
  • PS2 keyboard connector
  • Stereo audio out with low pass filter
  • RS232 serial output
  • Reset button
  • Jumper to configure VGA or RGBS mode

The board schematic was inspired by the following other designs

  • VGA, audio and PS2 part from Papilio Arcade Megawing
  • IEC serial bus from SD2IEC design
  • DRAM from Quickswitch QS3 voltage level translation application note AN-11A
  • RS232 from MAX232 application notes

I have used Eagle 6.2 to create board schematic and layout. Size of the board fits to the limitation of Eagle free edition. All traces of the PCB was manually routed by me then sent for manufacturing. SMD soldering of components were done by me without hot air gun.

The above mentioned features fully utilize free Papilio I/O ports so there is no space left for joystick connections or user port. This is a small drawback however the original goal was...

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FPGATED v1.1.zip

Joystick emulation added on PS2 keyboard numeric keypad. c16.v and c16_keymatrix.v modules are modified to implement joystick emulation. F11 selects between joy0 or joy1, numeric keypad directions are joystick directions, numeric 0 key is the fire button.

Zip Archive - 2.00 MB - 08/23/2016 at 20:05

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FPGATED v1.0.1.zip

Source files of FPGATED v1.0.1 Minor bug fix on c16.v

Zip Archive - 2.00 MB - 08/08/2016 at 21:52

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Papilio TED wing.zip

Eagle schematic and board files for Papilio TED wing

Zip Archive - 103.42 kB - 05/05/2016 at 09:24

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  • 1 × Papilio One 500K developer board Gadget Factory's Open Source FPGA development board based on the Xilinx Spartan 3E FPGA
  • 1 × Papilio TED wing An own designed and built wing for the Papilio One 500K board
  • 1 × VGA to Scart cable An own built RGBS video cable (same as Minimig scart cable)

  • Plus4 module with sdram controller and bootstrap

    István Hegedűs6 days ago 1 comment

    Development of FPGATED has not stopped! Although during this year I was slower than I expected I have a working PLus4 in FPGA which uses the Papilio Pro platform's sdram and onboard flash chip to store/upload ROMs. I am currently working on the improvement of the flash memory controller which can already load the Plus4 ROM images from the user data location of the FPGA external flash ROM chip during power up. I decided to create a special Kernal that will be load during power up when the user keeps a special key pressed. This Kernal will provide configuration options with which the user can configure ROM versions to use and turn on/off special hardware extensions like memory expansion, sid card, etc. ROM version registers and configuration registers however need to be written back to flash memory and this write routine does not exists at the moment. When I am ready with it I will publish the latest Plus4 wrapper top module with sdram controller and bootstrap modules.

  • Development progress update

    István Hegedűs11/14/2016 at 09:19 0 comments

    Hi all,

    I have been quiet recently however in the background I have not stopped development of FPGATED.

    Current focus is on creating a Plus4 version for Papilio Pro FPGA board. These are the statuses of my progress

    1. SDRAM controller for FPGATED using Papilio Pro's onboard sdram. Ready.

    2. Bootstrap to load ROM files from flash chip to sdram on startup. In progress.

    3. Implement Hannes/Csory ram expansion, plus develop new RAM extension method. Planned.

    The SDRAM controller works perfectly and makes use of the whole 8MB RAM of the Papilio Pro board. 4MB will be available as RAM for TED and 4MB for alternative ROM images (Original Kernal/Basic, Jiffy DOS, Function ROMS, Cartridge ROMS).

    I will release next code when point no 2 is done. Hopefully soon so come back to see.

    Istvan

  • FPGATED v1.1

    István Hegedűs08/23/2016 at 20:41 0 comments

    Finally joystick emulation is added to the FPGATED bundle. The main core ted.v is not changed, still on 1st release level , only c16.v and c16_keymatrix.v files have been modified. One joystick is emulated on the PS2 keyboard's numeric keypad similarly to fpga64. Keypad directions are the joystick directions and numeric 0 key is the fire. Use F11 to change between joy0 and joy1.

    An external real joystick port 's appropriate pins can be added easily to kbus product terms. in c16.v.

  • Bug fix in v1.0.1 version

    István Hegedűs08/08/2016 at 21:57 0 comments

    Original release has contained an incorrect c16_datalatch size in c16.v module. Xilinx ISE has corrected it automatically during synthesis however now it is fixed in v1.0.1

    Also reset function is improved. Now reset signal of CPU becomes active while user keeps reset button pressed.

  • Mist-FPGA port

    István Hegedűs07/25/2016 at 18:41 0 comments

    Porting FPGATED to Mist-FPGA has started!

    Check it out at http://mist-fpga.net/viewtopic.php?f=17&t=198&p=1048#p1048

  • FPGATED v1.0 Released

    István Hegedűs07/21/2016 at 21:07 0 comments

    FPGATED v1.0 released!

    Finally I have verified and packed all source files to a bundled and released it.

    Now FPGATED source files are downloadable!

    It would be good if someone from NTSC world could test it and report the results to me as I have never had a chance to get close to an NTSC monitor for testing.

  • Project update

    István Hegedűs06/28/2016 at 20:31 0 comments

    Sorry for the delays in releasing the source codes and finalize the description.

    I have not forgotten this project, the FPGA indeed works fine, I just could not find the time to clean up the code and release it in time. Latest by end of july I will release FPGATED 1.0 source codes!

    Stay tuned!

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István Hegedűs wrote 6 days ago point

Thanks for the nice feedbacks! Unfortunately this year I have slow down a bit due to several reasons but I have not forgotten the project. On the Papilio Pro platform I have created a Plus4 top module which loads Kernal, Basic and Function ROMs from the flash memory to sdram. This is the same flash memory which is used to store the FPGA bitsream. Currently I am working on the improvement of  flash memory controller which will make it possible to store FPGATED configuration registers (active ROM versions, memory expansion enable/disable, etc) and load them on power up. When this is ready I will make the code available and it will allow the port of the core to more platforms using sdram. HW development will continue after this. I want to make a 8501 drop in replacement and of course the TED drop in replacement as well!

  Are you sure? yes | no

Stinger wrote 04/04/2017 at 21:23 point

István, this is simply amazing what you've already achieved and to where you're looking forward. I think you know absolutely, what this project means for the entire 264 fanbase with a thousands of dead Plus 4/116/C16 machines (including myself, with a dead TED's in my Plus4 & C116). You can save them, revive them with the enthusiasm and excellence of your entire project. I think this is why this job (or calling it fanatism :) is so powerful.


Please let us know, If we can help you in anything for production, or manufacturing once you think that you reached a milestone. At AmigaSprit.hu forum a lot of talented and well-experienced hw developers are sharing their experiences about various homemade accelerators and other enhanced multi-produced hardware which were built on a very similar way like yours (not to mention our hardware tech folks at BME who were excited about your work when they heard about it. 

So again: kudos, can't wait to see more and best wishes from Budapest! :) 

In Hungarian: elképesztő amit elértél, hatalmas gratulációm! Remélem, hamarosan tesztelhetjük ezt az életmentő csodát. :)

  Are you sure? yes | no

zoltanmarkus wrote 03/18/2017 at 19:21 point

This is pure fantastic. I have 3 dead Plus/4, most probably with defective TEDs. I did not throw them out, though I know I could revive them only on the price of an other 264 series computer. Your project may help to revive some dozens of them, though I know for that you need factory or someone able to produce them cheap. (that is also a challenge).
Egy nagy gratula Nagykanizsáról, nem semmi projekt!

  Are you sure? yes | no

claude wrote 12/02/2016 at 10:38 point

This is fantastic!!, been waiting 10 years for a +4 SBC, PLZ, PLZ, PLZ, add user port support.

  Are you sure? yes | no

István Hegedűs wrote 12/03/2016 at 15:07 point

Although the original aim was to create the TED chip only, we cannot make much use of it without building a computer of it. Thus my sources include a C16 top module. At the moment I am working on a Papilio Pro version which will use the flash chip to store rom data and it will make possible to create a Plus4. The user port support should not be difficult as the 6529 code is already in the sources. I believe it is just a HW challenge, building an 5v translation for it. I am thinking on designing a PCB with a Spartan6 and that could have the user port too.

  Are you sure? yes | no

claude wrote 12/04/2016 at 09:00 point

honestly, this sounds very exciting, add me to the buy list

  Are you sure? yes | no

gertk wrote 08/01/2016 at 16:48 point

I would definitely leave in the CPU support since the CPU's of the C16 and Plus4 are about as delicate as the TED chips. Would be nice to have a small replacement board you could put in the TED socket, remove the CPU and have a reliable system.. I already did something similar with a Raspberry Pi replacing TED and CPU, Pi is programmed in 'Bare Metal' mode so it can boot up instantly. It has CVBS (through the original port) and HDMI video out. Keyboard is connected to GPIO pins so can be read directly too.

  Are you sure? yes | no

Peter Edwards wrote 11/22/2016 at 15:15 point

Sounds like an interesting project, do you have any links / further info?

  Are you sure? yes | no

István Hegedűs wrote 12/03/2016 at 15:02 point

Hi,
Currently this is my only page on it. I am planning to create a github page also soon in the near future.

  Are you sure? yes | no

Kilobytemagazine wrote 07/15/2016 at 07:26 point

Hi there, this looks great! Would like to know a bit more and write an article about this - please drop a line at kilobytemag[at]gmail[dot]com. Thanks!

  Are you sure? yes | no

István Hegedűs wrote 05/03/2016 at 16:31 point

Hi Jack,

This is the project I have mentioned to you once on one of the Papilio forums. In the coming weeks I will fill in all information and publish source codes. 

Stay tuned!

Istvan

  Are you sure? yes | no

Jack Gassett wrote 05/02/2016 at 22:40 point

This looks like a great project!

  Are you sure? yes | no

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