The purpose of this project is to design a set of logic circuit families using discrete transistors. I started with the idea of building a CPU or computer out of discrete components and searched the Internet for classic logic designs using Diode Transistor Logic. In my explorations I found a treasure-trove of information at and discovered documentation for the logic families used by IBM from the mid 1950s to the early 1970s, IBMs Standard Module System (SMS) boards and Solid Logic Technology (SLT) modules.

I was impressed with the simplicity of IBM’s Current Mode logic which is basically Emitter Coupled logic without emitter followers but there are a couple of issues with directly emulating these designs. First of all the IBM circuits were built using germanium transistors which are expensive and hard to find. So all of the voltage levels have to be recalculated to accommodate silicon. The second problem is that the input voltage levels to a current mode switch are not the same as the output levels. Modern ECL circuits use emitter followers to shift the output level to the required input levels. The IBM circuits didn’t use emitter followers but used complementary transistors, PNP based gates had to be followed by NPN transistor gates and vice versa. The problem is that even in silicon, high performance PNP RF transistors are becoming scarce so I’m using emitter followers. Using a mixture of old and new design approaches, I am starting out with an ECL logic family. My goal is to build a subsystem with enough complexity to explore system-level issues such as circuit board design, backplane design, and power distribution issues. 

Initially breadboarded the circuits using the “dead bug” approach which is commonly used for RF breadboarding. In “dead bug” construction, the circuit is built on a copper-clad circuit board that makes up the ground plane. I’m running the circuits at 40 MHz since I only have a 100 MHz scope. Once the designs are solid at 40 MHz, I’ll explore other clocking options and test at 80 MHz or even 100 MHz.

I plan to start out by experimenting with the following circuits:
1.) Basic current switch / ECL inverter and ECL clock source.
2.) TTL/DTL to ECL interface. This will allow me to build some test equipment and eventually interface to my own DTL logic. 
3.) Simple test fixture for logic testing.
4.) OR/NOR gate.
5.) Cascode or series logic AND/NAND gates and XOR/XNOR gate. Series logic is also used to clock flip-flops.
6.) JK Flip-Flop