Hackaday TTLers

Where DIY DIP/SSI/MSI CPU makers meet and discuss other TLA (three letters acronyms)

Public Chat
Similar projects worth following
I can't keep track of all the awesome "discrete" CPU designs on my own project. There is a list of such projects but it is "curated". Why not make my own list and invite like-minded hackers ?
If you have a similar project here, drop me a message and I'll add you to the contributors.

For practical reasons (it's impossible to list everything on the 'net), the "project" is mostly about gathering people from HaD who built their CPU (or at least digital electronic devices). Here are some external links for those who just can't get enough:

Feel free to suggest or add links of the same kind :-)

PS: the project's logo comes from Wikipedia

PPS: let's not forget the two lists and but note they are subject to curator delay (and taste).

1. Dynamic RAM with single MOSFET per bit ?
2. Bizarre DTL Logic Levels - The Discrete Component PDP-8
3. The Electronics of IBM Standard Modular System Logic
4. ECL or CTL : what's the fastest topology for discrete gates ? [updated]
5. TTL inside
6. Direct Coupled Transistor Logic
7. Interactive Simulations of DEC R-Series Logic
8. Why is ECL faster ?
9. Bipolar XOR gate with only 2 transistors
10. Video Explaining DEC R-Series DTL
11. The rule of 50 (or so)
12. Bipolar transistors are ANDN gates !
13. The return of CTL
14. From XOR to MUX
15. From MUX to Latch
16. Project proposal : Ring oscillators zoo !

DEC R-Series Logic Flip Flop.mp4

An animation of the operation of a DEC R-Series Logic Flip-Flop from a PDP-8 or early PDP-11

MPEG-4 Video - 2.04 MB - 07/04/2018 at 23:10


DEC R-Series Logic Inverter.mp4

An animation of the operation of a DEC R-Series Logic Inverter from a PDP-8 or early PDP-11

MPEG-4 Video - 692.53 kB - 07/04/2018 at 23:09


DEC R-Series Logic Inverter.txt

Import this circuit schematic description into this website (requires JavaScript):

plain - 1.19 kB - 07/04/2018 at 23:09


DEC R-Series Logic Flip Flop.txt

Import this circuit schematic description into this website (requires JavaScript):

plain - 3.73 kB - 07/04/2018 at 23:09


  • Project proposal : Ring oscillators zoo !

    Yann Guidon / YGDES03/14/2020 at 01:30 9 comments

    We TTLers love to test technologies, play with parts and explore new (or old !) realms. And one of the first things we do when we get our hands on a new transistor is see how fast they can go !

    For example:
    #Ring Oscillators: Fairchild DTL 949 by @Dana Myers
    CBJT ring oscillator by @Ted Yapo
    Relay ring oscillator
    I2L ring oscillator by @Dana Myers
    2N2369 ring oscillator / #Discrete Bipolar Logic (RTL/LTL)  by @Tim
    LTL ring oscillator by @Tim
    Emitter-Coupled Logic ECL ring oscillator by @Dana Myers
    74AC02 gated ring oscillator by @Ted Yapo
    BC548B 5 Stage Ring Oscillator by @agp.cooper
    (add yours here !)

    These days I'm contemplating "tasting" BFP740 (44GHz GBW but not in stock so far) and 2N2369 gates (I have a fistful but not enough to make anything interesting)...

    I propose to create a new project/page where we gather all the ring oscillators experiments, sort them by technologies, discuss on measurement details (and gotchas) and agree on a standard "size" to help tally and compare speeds, efficiencies etc.

    I was thinking that with my BFS480 (rated at 7GHz) I would need 9 inverters in series to have a reasonably observable waveform and a frequency that my HP5335A could accurately follow.

    Is anybody interested ?

  • From MUX to Latch

    Yann Guidon / YGDES01/31/2020 at 01:35 9 comments

    Edit : this exploratory page is interesting but not the final word. The rest is logged at More bistables...

    You know that a MUX can be easily turned into a latch by looping the output back to one input...

    And in  From XOR to MUX I turn a XOR into a MUX. So the next logical step is to connect the output to one of the inputs...

    The natural choice is to connect Y to A because the polarities are compatible.

    This is unfair for the /B input which is inverted and requires a pull-down transistor.

    My quest is to make a D-FlipFlop circuit with the least number of bipolar transistors. A pair of latches will require another NPN to pull /D low, but another topology is possible if complementary transistors are allowed :-) As in the early IBM ECL circuits (Current Steering Logic) I can make the next stage complementary to save one transistor... As a bonus, there is no need of a complementary clock signal and the output data has recovered its original polarity :-D

    Now, the more I look at it, the more I doubt it can work as is. There must be errors here and there...

    I'm sure the CLK signal will create quite a lot of problems and it must be split into overlapped, out-of-phase signals (2-phase clock ?)

    But I'll have to test and you know, you're never safe from a good surprise... who knows if it could be the basis of a new clock or UART ?

    Edit :

    @roelh  commented :

    • Normally, both transistors must invert the signal, but in your circuit one of them is an emitter follower that does not invert.

    "yes but" double inversion is not the real requirement for latching, it's a consequence that transistors can only invert. We can apply the which states : gain > 1 and phase = 0 (mod 2Pi). To fulfill this condition, you need 2 transistors because each adds a phase of Pi, and their gain is >1. However, most latches are used both in common emitter configuration, which creates the double inversion. Here I use another structure, similar to a SCR

    "It acts exclusively as a bistable switch, conducting when the gate receives a current trigger, and continuing to conduct until the voltage across the device is reversed biased, or until the voltage is removed" because I use the common collector output (borrowed from the classic ECL gates structures). My circuit is almost identical, I only added a base resistor to prevent damage and too hard a saturation. The phase is 0 and the gain is very high so latching should occur as long as the CLK level is enough (which will be another concern for later)

    • Personally I would design a transistor CPU in such a way that the registers are latches (that was also done by Dieter in his transistor CPU).

    I agree too : this cuts the transistor count in half and this is what is intended for #YGREC8.

    However it is necessary to see the full DFF working on the bench and be familiar with its idiosynchrasies, before I cut it in half. It's important because I'll have to decide which part is NPN and which part is PNP. Apparently here the first/common latch is PNP because there are fewer transistors, and the bulk (replicated for each register) would be NPN because I have more of these.

    The speed and timing of the circuit will depend on the power supply, the saturation and other parameters... I might have to add a anti-saturation diode in the SCR latch part, while the saturation of the emitter might not be such a problem. In fact, saturation is often considered in common emitter configurations, but here the emitter is a data input so I'm in a totally uncharted territory...

    And I would love to test the circuit in both Silicon and Germanium versions. I don't have Germanium NPN transistors though (or so few, eventually) so it would be interesting to find a solution with only a single type/polarity.

    Time to play with Falstad !!!

    So I played with Falstad for hours and came up with this simulation...

    Read more »

  • From XOR to MUX

    Yann Guidon / YGDES01/17/2020 at 01:59 3 comments

    You might remember my musings with the XOR gate with interlocked NPN transistors discussed at Bipolar XOR gate with only 2 transistors

    But thinking about how XOR is done with pass transistors in CMOS and the structure often creates a MUX, I wondered if I could translate this concept back to bipolar world.

    This first result is pretty nice and compact though the circuit is highly unbalanced...

    • A is a typical high-impedance input where a high signal is a valid 1.
    • /B is a negated low-impedance input that must be shorted to -V to make a valid 1. Another transistor can do the trick though that would create another delay...
    • Sel has to swing High and Low...

    But for discrete, parts-constrained circuits, that might work...

    The output could be used to directly drive another MUX stage if the next MUX swaps the NPN for PNP (and reverse polarity) though a big MUX could also be built with the single-transistor NPN-ANDN gate to then drive a big CTL AND gate.

    Has anyone seen this circuit before ?

    The MUX seems to work well on this Falstad simulation:

    Another Falstad sim was required to validate the enhancements : an additional transistor to de-invert /B can be useful...

    The source code is :

    $ 1 0.000005 10.20027730826997 50 5 43
    w 144 112 352 112 3
    v 144 400 144 112 0 0 40 3 0 0 0.5
    r 352 112 352 176 0 1000
    t 304 240 336 240 0 1 0.6163510467707772 0.6473024119705006 100
    t 416 240 384 240 0 1 -0.030951365199723496 0.027087887962126838 100
    t 352 304 384 304 0 1 0.6173128261844162 0.6352410780104729 100
    r 432 112 432 176 0 1000
    r 240 304 304 304 0 1000
    r 240 240 304 240 0 1000
    w 352 176 352 208 2
    w 336 224 336 208 0
    w 336 208 352 208 0
    w 352 208 384 208 0
    w 384 208 384 224 0
    w 144 400 336 400 0
    w 384 400 384 320 0
    w 384 288 384 256 0
    w 304 304 352 304 0
    L 240 304 208 304 0 1 false 3 0
    L 240 240 208 240 0 1 false 3 0
    L 240 368 208 368 0 1 false 3 0
    w 336 400 384 400 0
    w 336 352 336 256 0
    w 336 352 432 352 0
    w 416 240 432 240 0
    w 432 240 432 352 0
    t 304 368 336 368 0 1 0.6161066110712008 0.6611227508593843 100
    w 352 112 432 112 0
    w 432 240 432 176 0
    w 336 400 336 384 0
    w 464 208 384 208 0
    r 240 368 304 368 0 1000
    t 464 208 496 208 0 1 -2.924032495012093 0.07596750308398237 100
    w 432 112 496 112 0
    w 496 112 496 192 0
    r 496 288 496 400 0 1000
    w 384 400 496 400 0
    w 496 224 496 288 3
    38 18 2 0 3 B\sLow
    38 18 1 0 3 B\sHigh
    38 19 2 0 3 A\sLow
    38 19 1 0 3 A\sHigh
    38 20 2 0 3 CLK\slow
    38 20 1 0 3 CLK\shigh

    I have re-wired the B base resistor : it's now a pull-up that is shorted to 0V by the main SEL input. I added another transistor on the B input to get rid of the inversion (and some isolation).

    The output is inverted with an common collector output stage, though an open collector is also possible, it would re-invert the value and make it a non-inverting MUX.

    The select input and transistor can be shared by more than one MUX, which makes it an attractive solution for selecting a whole bus for example.

    Here is the non-inverting MUX with open collector output :

    So this is the version that would solve the problem found by @roelh  :-D

    And when you have a MUX2, you can cascade 3 of them to build a MUX4 :-)

    There are inversions here and there but some are opportunities to save a transistor.

  • The return of CTL

    Yann Guidon / YGDES09/18/2018 at 16:37 0 comments

    I found the original source of that story (ECL or CTL : what's the fastest topology for discrete gates ? [updated]) about "CTL" (Complementary Transistor Logic, which, since it doesn't invert, can't qualify as logic :-P )

    The author presents his TTL gate, then his modification inspired from TTL.

    I did some tests and tried a basic gate and... "it's a weird AND".

    More precisely it works as a linear amplifier with close to no voltage gain but strong current gain. When the circuit is rewritten, it's obviously a pair of complementary "emitter followers" with the output clamped above 2.5V-Vbe=1.7V. The output can go down to about 0.2V on my tests.

    This circuit also has a strong tendency to oscillate. My test setup was poorly designed but I could stop 60MHz oscillations with a 4n7F capacitor at the input of the PNP. I'll see how I can get a stable circuit...

    Since this is just a pair of emitter followers, why bother with using PNP inputs after all ? With my BC559C, each with hFE=480, the overall gain is about 200K, the input current is very low but this is overkill and oscillations are not surprising at all.

    The PNP emitter followers at the input are nice. The NPN emitter follower at the output is nice. AND gates are very useful in some places. However this is not what we expect from a "logic gate" because there is no real "active level" or "threshold". Current gain is nice but voltage gain is important too ! So this CTL might be faster than ECL but ECL can do more functions and provide inversion.

    Furthermore, it looks quite a lot like the Low Offset Emitter Follower :

    After this little setback (or disappointment) I looked at other ways to make this circuit and a variation appeared : it replaces selected PNP input transistors with NPN.

    Thus instead of inverting the output, we can invert the necessary input(s) and we apply "bubble pushing" :-)

    Of course the logic levels are modified but this leads to the interesting concept of a cascade of emitter followers, "or-dotted" together for the OR functions, with parallel transistors for AND or OR functions, and complementation (switching from PNP to NPN and vice versa) for the negation.

    Of course we can also use BJT as ANDN gates :-)

  • Bipolar transistors are ANDN gates !

    Yann Guidon / YGDES09/10/2018 at 12:41 3 comments

    In the log Bipolar XOR gate with only 2 transistors  we see the legendary interlocked transistor gate :

    Then this  HAD post   describes a very clever driving scheme :

    Then it became clear... Under the right driving situation, a transistor (with its base resistor) is a ANDN gate !

    Why does it matter ? Because this could greatly help to implement circuits such as this 7-segments decoder:

    This is a sort of "slow" circuit where parts count matters more than speed (hard saturation is not an issue) so hacks like this will help a lot :-)

    For the above "arbitrary logic" array, wired-oring will also save parts. All we have to do is "solve/reduce with ANDN". Who wants to play that game with me ? :-D

  • The rule of 50 (or so)

    Yann Guidon / YGDES09/10/2018 at 12:27 10 comments

    [updated 20180930, read the comments below for more background]

    People usually confuse the operating frequency of the computer with the max. frequency of its individual parts.

    Let's say a CPU runs at 1GHz, that must mean each transistor switches 1 billion times per second, right ? Hahaha I'm kidding.

    Actually the Ft (transition frequency) of transistors is way higher than that. And the whole circuit is slowed down by other factors such as wires, capacitances, resistances that make distributed RC networks along with the capacitances, and countless other factors. Of course, the CDP (critical datapath) length matters too.

    But in average, I have observed a 1:50 ratio between the operating frequency of a processor versus the "speed" of the constituting transistors, for reasonable architectures. This might be lower for recent ultrapipelined processors but when you make your own discrete processor, divide the Ft by 50 to get your final processor's speed. A ratio of 100 is much more realistic for a hobby project but it's less optimistic...

    The ratio of 50 is a realistic ceiling that shows the influence of parameters outside the transistor's ideal characteristic. One such influence is the type of logic gate (TTL, DTL, CTL, DCTL, ECL...) so you have to measure your individual inverter gate speed (for example with a ring oscillator) for a better estimate.

    I'd be happy to get more datapoints from various architectures and implementations. A chart would help us identify the factors that inflate or decrease this ratio and give us a better prediction.

    Note : this rule applies to transistors and semiconductors, not relays, where the delay is limited essentially by the contact switching speed and RC delays are irrelevant.

  • Video Explaining DEC R-Series DTL

    Blair Vidakovich09/07/2018 at 03:40 3 comments

    Hey! I have made a short home-made video explaining an alternate form of DTL.

    Click on the image below to view the video!

    Video URL:


  • Bipolar XOR gate with only 2 transistors

    Yann Guidon / YGDES07/29/2018 at 15:49 26 comments

    I sometimes find a small circuit with 3 resistors and 2 transistors that performs the eXclusive OR operation.

    These two interlocked transistors use a very unusual structure, which requires the least theoretical number of switching elements, but it depends on a trick : the input impedances matter a lot and the circuit depends on a "hard" 0 level, because the circuit behaves almost like a "pass" element...

    Thus, the question : is it the best method ? What about the switching speed or the capacitances ?

    XOR is pretty important in CPUs because many mechanisms rely on it, for example ALUs. Does the gain in parts count affect the performance ? Apparently, it's pretty close to ideal because it's touted as a solution in Direct Coupled Transistor Transistor Logic:

    Another version has only one transistor but 4 diodes :

    Another question is : can this scheme (no amplification, just relying on the input's strength) be extended to other logic or sequential functions ?

    The XOR gate has a much wider range of implementations in MOS and CMOS. You can find circuits using 4, 6, 8, 9, 10 or 12 transistors, again with varied strengths for the inputs and the output. For example, pass-transistor logic (transmission gates) makes it pretty simple :

    Each pass element is a pair of complementary transistors, so this gate uses 2 NMOS and 2 PMOS. Add as many if you want to isolate the outputs with inverters...

    Oh and don't forget another inverter at the output. This is why you'll find various transistor counts. Unless the designer wants to decompose the function into elementary boolean functions, and the size explodes, depending on how you break it up:

    (also missing : picture with MUX2 and an inverted input)

    This decomposition leads to the "classic" CMOS XOR gate:

    which gains weight again when the inputs are buffered and inverted :

    XOR has a reputation of a "slow and large gate" for this reason and that's why I investigate smarter topologies and their compromises.

    Another version is also pretty nice :

    This is interesting for my #Yet Another (Discrete) Clock because it is almost suitable for MOSFETs. The B input must double the transistors because of the inherent diodes but it's "only" 3×BS170 and 3×BS250. In this case, the B input actually works as a multiplexer or transmission gate... Which means it might not be suited for ultra high speed.

    Even fewer parts with this 3T XOR :

    In this case, only 1×BS170 and 3×BS250  are required. It's still not ideal because the BS250 is more expensive than the BS170 but I don't see how to permute the polarities without requiring more inverters... Furthermore, there seems to be a conflict with one of the input combinations : B=1 forces the output to 0, but if A=0 then the input B (which is =1) is forced to 0 by itself... The solution is another PFET controlled by A, in series with the grounding NFET.

    Another source explains in great detail why the short circuit is not such a big deal for ICs : they tune the width/ratio of certain transistors to minimize the unwanted current. This trades space for power consumption.

    M1 has a 1/1 ratio, almost a square, wih minimal size, hence highest resistance, while M3 has a high ratio to overcome the pull-down from M1. For very high-speed CMOS circuits, where power is dominated by switching (and leakage for the newest processes) this short current can be considered "negligible".

    Another interesting compromise uses only 2 of each type:

    But the "upper pass trick" on input A might still need doubling of the P-MOSFET to cancel the parasitic body diodes. This could be cheaper if XNOR was made instead, so 2 PFETs are tied to Vcc in series, and the NFETs are used as pass elements.

    ICs use even more variations on these ideas:

    This odd one seems to interlock the leftmost...
    Read more »

  • Why is ECL faster ?

    Yann Guidon / YGDES07/12/2018 at 11:25 9 comments

    Lately I was looking for very fast diodes to design faster DTL/TTL discrete gates.

    • silicon epitaxial diodes can be quite fast but still have a limited frequency of rectification (particularly the cheap ones).
    • As noted by @K.C. Lee on #YGREC-ECL : "Carrier mobility isn't as good as electrons.  That's why NPN, N-MOSFET
      have better performance than their PNP, P-MOSFET counterparts.
      " so a complementary TTL gates, with a PNP input stage, would probably be speed-limited by the input transistors.

    @Al Williams just released an article on :

    The recovery time makes a difference in several designs including switching power supplies. If you dig into the physics, there is a usually a trade-off between several other parameters and recovery time. Just to give you an idea, the datasheet for a BAT42 Schottky diode says the reverse recovery time at 10mA is no more than 5 ns."

    I don't know the exact figures in practice in a logic gate but 5ns of recovery is not good. That's about the propagation time of a DCTL inverter in the CDC6600.

    Rectification speed was already a burning subject in the 40s because it was essential to the war effort (faster diodes means higher carrier frequencies, shorter wavelengths and better radar resolution)

    ECL prevents all these issues because

    1. there are only NPN transistors
    2. no diode (no recovery time)
    3. no saturation

    However there are more transistors... so maybe DCTL is an interesting alternative ?

  • Interactive Simulations of DEC R-Series Logic

    Blair Vidakovich07/04/2018 at 23:15 3 comments

    For those interested in visualising the operation of DEC R-Series Logic, I have created these two short animations which simulate the operation of an Inverter and a Complementing Flip-Flop:



    You can find the schematic files for these simulations saved here:

View all 16 project logs

Enjoy this project?



Yann Guidon / YGDES wrote 03/14/2020 at 17:17 point

Our friend @Artem Kashkanov  in München museum of computers :

Thanks for sharing :-)

  Are you sure? yes | no

Artem Kashkanov wrote 03/14/2020 at 17:58 point

Huh... Now I need to add normal subs :D

  Are you sure? yes | no

Yann Guidon / YGDES wrote 03/14/2020 at 18:12 point

of course !
you won't let us miss this awesome visit, right ? ;-)

  Are you sure? yes | no

Yann Guidon / YGDES wrote 03/05/2020 at 00:46 point

I've come across a type/family of CMOS logic gates called "TSPC"

"True Single Phase Clock" latches

I can't yet wrap my head around it but it's fascinating...

  Are you sure? yes | no

Tim wrote 03/05/2020 at 05:50 point

Isn't that the, more or less, standard way of doing edge triggered flip flops in CMOS?

  Are you sure? yes | no

Yann Guidon / YGDES wrote 03/05/2020 at 06:19 point

it seems to be a whole family of design techniques for dynamic latches.
The static latches (using flip-flops, feedback, muxes...) are more common in the litterature. I know CMOS design stuff for more than 20 years and have heard about "domino logic" and other "precharged" gates but they are usually frowned upon, unless you have total control of the fab process...

  Are you sure? yes | no

Tim wrote 02/27/2020 at 06:25 point

Since there is a lot of discussion about exotic bipolar logic here... I have never seen any mention of I²L:

It's much more useful in an integrated circuit, though.

  Are you sure? yes | no

Yann Guidon / YGDES wrote 02/27/2020 at 09:43 point

yes I discovered it here too :-)

I wish there were discrete transistors with multiple collectors...

  Are you sure? yes | no

Tim wrote 03/01/2020 at 10:35 point

In I²L they actually use emitter diffusions for the collectors. Will result in a low hfe, but it means that the problem actually reduces to finding discrete multi-emitter transistors.

One of the original papers* on I²L actually shows an implementation example where light is used for the current injection.


(why on earth is the nesting depth of comments limited!?! Can't respons to Yann)

  Are you sure? yes | no

Yann Guidon / YGDES wrote 03/01/2020 at 15:17 point

@Tim that would be a very interesting read if you can find it :-)

  Are you sure? yes | no

Yann Guidon / YGDES wrote 03/05/2020 at 00:48 point

Thanks @Tim !!!

  Are you sure? yes | no

Yann Guidon / YGDES wrote 03/05/2020 at 07:00 point

Now if only that document was not paywalled :-(

  Are you sure? yes | no

Yann Guidon / YGDES wrote 02/17/2020 at 18:56 point

In case you didn't know already ;-)

  Are you sure? yes | no

Tim wrote 02/14/2020 at 21:50 point

I wrote an article about fast bipolar switching transistors for RTL. Looking at the transistors used on most of the RTL and DTL projects, this should be of interest to you:

Actually I made neat progress on RTL and DTL/LTL designs. Will try to publish more here

  Are you sure? yes | no

Ken Yap wrote 02/14/2020 at 22:15 point

Thanks, that CDC6600 article is an interesting read even though I have no intention to experiment with old logic technologies. Also thanks for the blog post on 3¢ MCUs. The Padauk looks interesting now that there is toolchain, although the saving over 20¢ STM8S is not yet compelling for my uses.

  Are you sure? yes | no

Tim wrote 02/14/2020 at 22:25 point

Yeah, I also thought I would just play around with ancient circuit design a bit... :) 

  Are you sure? yes | no

Yann Guidon / YGDES wrote 02/15/2020 at 21:25 point

Welcome Tim !
and thanks for bringing the CDC6600 back to the stage's front (i'm also a Cray admirer ;-) )

Oh I I thought it was the 2369 that was used by CDC, I'm not sure I've heard of the 709...

  Are you sure? yes | no

Tim wrote 02/16/2020 at 05:12 point

Thanks! Well, it took me quite a while to connect all the dots, although all the information is out there... Originally I found the 2369 via Nexperias product selector and was happy to have something that performed much better than the vanilla 847/3904. Good thing I did some simulation before diving into a build.

The knowledge about switching transistors seems to be something very obscure nowadays, otherwise it's hardly explainable why all RTL/DTL projects on the web insist on using suboptimal transistors? The 2369 comes in the same form factors and at almost the same price as the alternatives.

  Are you sure? yes | no

Yann Guidon / YGDES wrote 02/17/2020 at 18:58 point

At least now the search engines have one more reference to provide when asked about your interrogations :-)

  Are you sure? yes | no

Warren Toomey wrote 03/26/2019 at 02:50 point

(I posted a question but I think in the wrong area... try again!) I'm building a 16-bit tri-state program counter using 7400-family chips. I'm stuck with four 74HC161 4-bit counters and two 74HC241 8-bit buffers. Anybody know a way to reduce the chip count here, with TTL-level DIP devices? Need to increment, load, hold value & tri-state.

  Are you sure? yes | no

Alastair Hewitt wrote 03/26/2019 at 11:04 point

The 74ALS561 is a 4-bit counter with tri-state. This would eliminate the need for the two buffers.

If you didn't need to load then the 74HC590 gives you an 8-bit counter with tri-state in one chip.

  Are you sure? yes | no

roelh wrote 03/26/2019 at 11:41 point

But that's expensive, almost $6 at Mouser...

  Are you sure? yes | no

Julian wrote 07/11/2018 at 06:15 point

Just thought I should leave this here: can't say I've ever seen these before...

... 74181s *in a narrow DIP package* :)

  Are you sure? yes | no

Dave's Dev Lab wrote 07/11/2018 at 17:00 point

funny you should post that, as i picked up two of these at a surplus shop last week. it was the first time i had seen the 181 in that package!

  Are you sure? yes | no

Olivier Bailleux wrote 02/11/2018 at 08:39 point

Do you know the ?

  Are you sure? yes | no

Yann Guidon / YGDES wrote 02/13/2018 at 05:40 point

who doesn't ? :-)

  Are you sure? yes | no

Dylan Brophy wrote 02/13/2018 at 06:15 point

true :-D

  Are you sure? yes | no

Yann Guidon / YGDES wrote 02/13/2018 at 16:10 point

Actually, it is listed, but with the old address. I'm updating the details page now.

  Are you sure? yes | no

Frank Buss wrote 11/06/2017 at 00:01 point

I designed a simple CPU some years ago, optimized for running Forth:
The prototype worked in a FPGA.

  Are you sure? yes | no

Yann Guidon / YGDES wrote 11/06/2017 at 00:14 point

you cheated then ;-) what keeps you from building it out of discrete transistors like the #AYTABTU - Discrete Computer  or #ED-64: A discrete 8-bit computer ? :-P

  Are you sure? yes | no

Frank Buss wrote 11/06/2017 at 00:43 point

I guess I could do this, but this would be another week long project, and I have already so many unfinished projects :-)

  Are you sure? yes | no

tomtibbetts wrote 11/05/2017 at 21:54 point

Hi, maybe this is not the correct forum.  But I have an issue with ringing on clock pulses.  I am building a SAP 1 computer on PCBs ( and the clock circuit is producing clock pulses that sometimes have a bit of ringing on both the rising and trailing edges of the pulse.  it doesn't happen all the time but there does seem to be a pattern to it.  One of the clocks is used for the sequencer and the other is for clocking all the registers.  Because of the ringing, the counters sometimes get double clocked and will skip a count.  What would be causing this?  Any help is appreciated.  Thanks

  Are you sure? yes | no

Yann Guidon / YGDES wrote 11/05/2017 at 22:55 point

It would be a good idea to detail everything in a log (or more) on the project's page, because so far, the only answer I can give is to try to add a series resistance, add a 100ohms adjustable in series and check the bounces with a scope to see which impedance matches your tracks ?
Also : make sure you have a balanced and clean clock tree to prevent crazy matching problems.

  Are you sure? yes | no

Marcel van Kervinck wrote 11/06/2017 at 12:15 point

I found this document helpful, specifically figure 17.

For my computers I found there is some more ringing with FETs (74HCT) than with bipolars (74LS). But it never caused misbehaviour and I see no clipping, so I'm still with architecture (a) on my boards. I was prepared to add series resistors (option c) as a possible counter measure.

  Are you sure? yes | no

Yann Guidon / YGDES wrote 09/23/2017 at 13:53 point

@256byteram , @Peter Bosch , @Tony Robinson  and @John Croudy  are still invited to the project :-)

  Are you sure? yes | no

Yann Guidon / YGDES wrote 09/23/2017 at 02:38 point

Oh I missed that one :-D

  Are you sure? yes | no

Bill Rowe wrote 07/11/2017 at 20:23 point

Hi: Is there such a thing as a practical logic minimizer?  Something where you would feed in a truth table with N inputs and M outputs and get out a configuration of 7400/4000 chips that would implement it?

  Are you sure? yes | no

Ed S wrote 07/11/2017 at 20:28 point

Maybe Project Icestorm would do it? I know that with Xilinx' tools it's possible to get a logic netlist - not 7400, but logic gates. See

  Are you sure? yes | no

jaromir.sukuba wrote 07/12/2017 at 08:24 point

Take a look at Logic Friday -

You enter logic table, software spits out schematics made of logic gates of your choice. I used that thing when designing my #Fourbit

  Are you sure? yes | no

Dr. Cockroach wrote 07/12/2017 at 08:51 point

Thanks Jaromir for the link to Logic Friday, looks like a tool I can use for my project :-)

  Are you sure? yes | no

Bill Rowe wrote 07/12/2017 at 10:51 point

Excellent - thanks.  I'll have a look.

  Are you sure? yes | no

agp.cooper wrote 09/23/2017 at 06:48 point

I use Logic Friday. It is a GUI for Expresso. It has a 16 input/output limit so beyond that you need to go directly to Expresso (I use a bat/cmd file). It optimises for generic gates packages or die-area.

  Are you sure? yes | no

Yann Guidon / YGDES wrote 01/11/2017 at 21:00 point

The list is growing. It feels good to be surrounded by so many ace designers !

  Are you sure? yes | no

Yann Guidon / YGDES wrote 03/25/2016 at 23:06 point

Wow we are already 11 TTLers ! 3 have not yet accepted the invitation though.

  Are you sure? yes | no

Dr. Cockroach wrote 12/22/2016 at 22:28 point

Thank you for the invite, I'm in :-)

  Are you sure? yes | no

Similar Projects

Does this project spark your interest?

Become a member to follow this project and never miss any updates