Hackaday TTLers

Where DIY DIP/SSI/MSI CPU makers meet and discuss other TLA (three letters acronyms)

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I can't keep track of all the awesome "discrete" CPU designs on my own project. There is a list of such projects but it is "curated". Why not make my own list and invite like-minded hackers ?
If you have a similar project here, drop me a message and I'll add you to the contributors.

For practical reasons (it's impossible to list everything on the 'net), the "project" is mostly about gathering people from HaD who built their CPU (or at least digital electronic devices). Here are some external links for those who just can't get enough:

Feel free to suggest or add links of the same kind :-)

PS: the project's logo comes from Wikipedia

PPS: let's not forget but curators are often quite picky and slow.

1. Dynamic RAM with single MOSFET per bit ?

  • Dynamic RAM with single MOSFET per bit ?

    Yann Guidon / YGDES08/20/2016 at 22:54 24 comments

    RAM is one big problem for "discrete projects". It must be fast, large and cost-effective. There are many types of discrete RAM but none that is based on discrete MOSFET (yet).

    Integrated DRAM uses MOSFETs but they differ from the discrete form because of the intrinsic diode with the substrate : it takes two discrete MOSFET to make one normal MOSFET. This would not be cost-effective to use discrete MOSFET to implement classic DRAM circuits.

    I found inspiration with the diode-capacitor cell described for the TIM computers :

    Diode-capacitor dynamic memory

    I can't figure out what capacitance was used in the relay-based TIM8. However, with a MOSET-based circuit, the capacitance can be greatly reduced (to 100nF for example) because the required trigger energy is considerably lower. I even have a reel of dual Schottky diodes in SOT23. But I'm not sure about the leakage...

    Now, a good MOSFET has a pretty low leakage. I have played around (on paper) and have come up with a topology that replaces the diode with a MOSFET. The gate capacitance is not used but the parasitic diode is !

    Each access cycle takes 2 steps:

    • Read and empty the storage capacitor: drive RD high => This pushes the capacitor's lower electrode high, which is then read on the Data line. Probably a threshold current is required to read a "1".
    • Write the value: drive the desired level on the Data line, drive RD to 0V and WR to 1 (let the current flow to RD so the lower electrode is 0V).

    It's funny that the read phase works a bit like a charge pump...

    Data, RD and WR are totem-pole (complementary) drivers. I will have to try different circuits for the sense. The line and column select (demultiplexers) will need a lot of transistors too... But at least it's more compact than the only other MOSFET RAM that I know :-)

    Now I wonder what should be the refresh frequency...

    Any comment/remark/historical perspective ?

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Yann Guidon / YGDES wrote 01/11/2017 at 21:00 point

The list is growing. It feels good to be surrounded by so many ace designers !

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Yann Guidon / YGDES wrote 03/25/2016 at 23:06 point

Wow we are already 11 TTLers ! 3 have not yet accepted the invitation though.

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Mark Nesselhaus wrote 12/22/2016 at 22:28 point

Thank you for the invite, I'm in :-)

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