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Hackaday TTLers

Where DIY DIP/SSI/MSI CPU makers meet and discuss other TLA (three letters acronyms)

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I can't keep track of all the awesome "discrete" CPU designs on my own project. There is a list of such projects but it is "curated". Why not make my own list and invite like-minded hackers ?
If you have a similar project here, drop me a message and I'll add you to the contributors.

For practical reasons (it's impossible to list everything on the 'net), the "project" is mostly about gathering people from HaD who built their CPU (or at least digital electronic devices). Here are some external links for those who just can't get enough:

Feel free to suggest or add links of the same kind :-)

PS: the project's logo comes from Wikipedia

PPS: let's not forget https://hackaday.io/list/2402-homebrew-computers but curators are often quite picky and slow.


Logs:
1. Dynamic RAM with single MOSFET per bit ?

  • Dynamic RAM with single MOSFET per bit ?

    Yann Guidon / YGDES08/20/2016 at 22:54 28 comments

    RAM is one big problem for "discrete projects". It must be fast, large and cost-effective. There are many types of discrete RAM but none that is based on discrete MOSFET (yet).

    Integrated DRAM uses MOSFETs but they differ from the discrete form because of the intrinsic diode with the substrate : it takes two discrete MOSFET to make one normal MOSFET. This would not be cost-effective to use discrete MOSFET to implement classic DRAM circuits.

    I found inspiration with the diode-capacitor cell described for the TIM computers :

    Diode-capacitor dynamic memory

    I can't figure out what capacitance was used in the relay-based TIM8. However, with a MOSET-based circuit, the capacitance can be greatly reduced (to 100nF for example) because the required trigger energy is considerably lower. I even have a reel of dual Schottky diodes in SOT23. But I'm not sure about the leakage...

    Now, a good MOSFET has a pretty low leakage. I have played around (on paper) and have come up with a topology that replaces the diode with a MOSFET. The gate capacitance is not used but the parasitic diode is !

    Each access cycle takes 2 steps:

    • Read and empty the storage capacitor: drive RD high => This pushes the capacitor's lower electrode high, which is then read on the Data line. Probably a threshold current is required to read a "1".
    • Write the value: drive the desired level on the Data line, drive RD to 0V and WR to 1 (let the current flow to RD so the lower electrode is 0V).

    It's funny that the read phase works a bit like a charge pump...

    Data, RD and WR are totem-pole (complementary) drivers. I will have to try different circuits for the sense. The line and column select (demultiplexers) will need a lot of transistors too... But at least it's more compact than the only other MOSFET RAM that I know :-)

    Now I wonder what should be the refresh frequency...

    Any comment/remark/historical perspective ?

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Frank Buss wrote 11/06/2017 at 00:01 point

I designed a simple CPU some years ago, optimized for running Forth:
http://www.frank-buss.de/forth/cpu1/
The prototype worked in a FPGA.

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Yann Guidon / YGDES wrote 11/06/2017 at 00:14 point

you cheated then ;-) what keeps you from building it out of discrete transistors like the #AYTABTU - Discrete Computer  or #ED-64: A discrete 8-bit computer ? :-P

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Frank Buss wrote 11/06/2017 at 00:43 point

I guess I could do this, but this would be another week long project, and I have already so many unfinished projects :-)

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tomtibbetts wrote 11/05/2017 at 21:54 point

Hi, maybe this is not the correct forum.  But I have an issue with ringing on clock pulses.  I am building a SAP 1 computer on PCBs (https://hackaday.io/project/26018-sap-1-computer-on-printed-circuit-boards) and the clock circuit is producing clock pulses that sometimes have a bit of ringing on both the rising and trailing edges of the pulse.  it doesn't happen all the time but there does seem to be a pattern to it.  One of the clocks is used for the sequencer and the other is for clocking all the registers.  Because of the ringing, the counters sometimes get double clocked and will skip a count.  What would be causing this?  Any help is appreciated.  Thanks

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Yann Guidon / YGDES wrote 11/05/2017 at 22:55 point

It would be a good idea to detail everything in a log (or more) on the project's page, because so far, the only answer I can give is to try to add a series resistance, add a 100ohms adjustable in series and check the bounces with a scope to see which impedance matches your tracks ?
Also : make sure you have a balanced and clean clock tree to prevent crazy matching problems.

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Marcel van Kervinck wrote 11/06/2017 at 12:15 point

I found this document helpful, specifically figure 17. http://www.ti.com/lit/an/scaa082a/scaa082a.pdf

For my computers I found there is some more ringing with FETs (74HCT) than with bipolars (74LS). But it never caused misbehaviour and I see no clipping, so I'm still with architecture (a) on my boards. I was prepared to add series resistors (option c) as a possible counter measure.

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Yann Guidon / YGDES wrote 09/23/2017 at 13:53 point

@256byteram , @Peter Bosch , @Tony Robinson  and @John Croudy  are still invited to the project :-)

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Yann Guidon / YGDES wrote 09/23/2017 at 02:38 point

Oh I missed that one :-D http://recursion.jp/comp/e/

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Bill Rowe wrote 07/11/2017 at 20:23 point

Hi: Is there such a thing as a practical logic minimizer?  Something where you would feed in a truth table with N inputs and M outputs and get out a configuration of 7400/4000 chips that would implement it?

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BigEd wrote 07/11/2017 at 20:28 point

Maybe Project Icestorm would do it? I know that with Xilinx' tools it's possible to get a logic netlist - not 7400, but logic gates. See http://www.clifford.at/icestorm/

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jaromir.sukuba wrote 07/12/2017 at 08:24 point

Take a look at Logic Friday - http://sontrak.com/

You enter logic table, software spits out schematics made of logic gates of your choice. I used that thing when designing my #Fourbit

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Dr. Cockroach wrote 07/12/2017 at 08:51 point

Thanks Jaromir for the link to Logic Friday, looks like a tool I can use for my project :-)

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Bill Rowe wrote 07/12/2017 at 10:51 point

Excellent - thanks.  I'll have a look.

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agp.cooper wrote 09/23/2017 at 06:48 point

I use Logic Friday. It is a GUI for Expresso. It has a 16 input/output limit so beyond that you need to go directly to Expresso (I use a bat/cmd file). It optimises for generic gates packages or die-area.

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Yann Guidon / YGDES wrote 01/11/2017 at 21:00 point

The list is growing. It feels good to be surrounded by so many ace designers !

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Yann Guidon / YGDES wrote 03/25/2016 at 23:06 point

Wow we are already 11 TTLers ! 3 have not yet accepted the invitation though.

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Dr. Cockroach wrote 12/22/2016 at 22:28 point

Thank you for the invite, I'm in :-)

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