Hackaday TTLers

Where DIY DIP/SSI/MSI CPU makers meet and discuss other TLA (three letters acronyms)

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I can't keep track of all the awesome "discrete" CPU designs on my own project. There is a list of such projects but it is "curated". Why not make my own list and invite like-minded hackers ?
If you have a similar project here, drop me a message and I'll add you to the contributors.

For practical reasons (it's impossible to list everything on the 'net), the "project" is mostly about gathering people from HaD who built their CPU (or at least digital electronic devices). Here are some external links for those who just can't get enough:

Feel free to suggest or add links of the same kind :-)

PS: the project's logo comes from Wikipedia

PPS: let's not forget but curators are often quite picky and slow.

1. Dynamic RAM with single MOSFET per bit ?

  • The Electronics of IBM Standard Modular System Logic

    Blair Vidakovich03/27/2018 at 06:07 8 comments


      Okay! We’ve had a look at the Diode-Transistor Logic of the DEC R-Series Logic, but that isn’t the only electronic logic system that was employed in building discrete discrete component computers. As I explained in the post on R-Series logic, back in 2013 it was some IBM computer which implemented an exotic electronic logic system which lead me to go down the “popular” DTL path. I will continue my investigation into different logic systems in this post with the IBM Standard Modular System (SMS) logic. IBM SMS logic doesn’t just implement specific systems of logic families, but also whole different logic families! The IBM SMS uses what is now known as Emitter-Coupled Logic (ECL), as well at Resistor-Transistor (RTL) logic and DTL. ECL is a very difficult logic family, and RTL is unpopular in hacker circles, so we will look at the IBM SMS DTL logic implementation first, and then just look at their ECL circuits. The Don Lancaster RTL Cookbook is sufficient really for people who wish to build discrete component RTL computers.

      IBM Standard Modular System Diode-Transistor Logic

      I have obtained the electronic description of the different IBM logic implementations from the IBM Transistor Component Circuits volume of the Customer Engineering Manual of Instruction. You can find this manual easily by searching the above words on the internet. There are also manuals describing the exact electronic schematics of the flip-chip cards used in IBM mainframes such as the 7070 and the 7090. They’re worth a look if you want some inspiration for solving a particular concrete problem.

      Logic Levels

      The SMS DTL system uses four different logic levels. They are divided into two fundamental kinds, “T” line levels and “U” line levels.

      The IBM SMS DTL Logic Levels

      As you can see, positive T levels swing from -0.7V to 6.0V, whereas negative T levels swing from 1.4V to -6.0V. Positive U levels go from 0V to -7.4V, and negative U levels move from -5.3V to -12V. There are schematics in the Transistor Component Circuits manual for how to convert T and U lines to each other. They’re not worth mentioning here because we don’t need to get into that much detail.

      The Fundamental Gates

      Below you can find the schematic for the fundamental positive-logic NAND gate, or negative-logic NOR gate. IBM doesn’t use the standard terminology for these gates, probably because the manuals for this system were written in the late-50s early-60s, before the terminology settled to what we know today. You’ll also notice that the symbols for transistors here are also non-standard by contemporary wisdom. The same reason should apply here. We won’t concern ourselves here with the physical electronic characteristics of the transistors and the diodes. I’ll put some work into that later.

      The IBM SMS DTL Basic Gates

      There are three gates specified here. As you can see:

      1. It is possible to interface the output of a DTL gate into ECL gates.
      2. The first gate (at the top) takes a +U logic level and outputs a -T logic level.
      3. The second gate (Gate “A”) takes a +U input and outputs a +T logic level.
      4. The third gate (Gate “B”) is similar to the first one: it recieves a +U level, and outputs a -T level, as well as being able to interface with ECL gates.

      It is possible to take T-line inputs and output U-line logic:

      The IBM SMS DTL U-line Output

      These gates can drive ECL gates as well! Note well that the T-line inputs for the above gates are NEGATIVE T line levels (-T levels).

      There are other inverters specified in this manual, such as “Power Inverters”, which drive bigger loads and have bigger gate fan-outs. You can peruse the manual to look at those at your leisure.

      There are also emitter-follower gates, which amplify the current of signals. There are also circuits for driving indicators connected to T and U line signals.

      Basic Flip-Flops

      Below you can find the schematic for a basic IBM SMS flip-flop:

      IBM SMS Flip-Flop

      This complex flip-flop...

    Read more »

  • Bizarre DTL Logic Levels - The Discrete Component PDP-8

    Blair Vidakovich03/26/2018 at 05:04 5 comments


    Hello! This is Blair Vidakovich. I was recently given entry into the hackaday TTLers group! I have tried many times, unsuccessfully, to create a discrete component computer. My basic logic element was a NAND gate, and I was using a popular form of DTL logic unit. I was copying the same electronic schematic as the Tiny Tim DTL computer. You can find the research and build log for this abandoned project here: ( Anyway this was my basic logic element, the NAND on the far right.

    I got stuck trying to build a ring counter, which I suppose I would use for control signals. I now see that a ring counter was not necessary, because many TTLers have gotten away with functioning discrete component computers without ring counters. In fact many people have successfully built four-phase clocks, so I now don't really need to worry at all, because the problem has been solved for me! 

    The reason why I got stuck was because I was attempting to build a DTL edge-triggered D flip-flop, and no matter how I tried, I could not build one that contained SET and RESET terminals. I could build one with just a clock and an INPUT terminal, but I could not go any further:

    Enter the Discrete-Component PDP-8

    I started researching and building a discrete component CPU/computer when I was diagnosed with schizophrenia in July 2013. The level of detail and concentration you have to come to master prevented me from getting any more delusional. I gave up the project when I started my PhD in 2015. I made another attempt to make a four-phase clock in 2016, but I failed again.

    Then when I returned to this project a month ago (Feb 2018), I remembered I came across some schematics for an old discrete-component IBM computer back in 2013, but balked at the idea of using their basic logic element because it used so many bizarre voltages. "It used negative voltages!" I thought. There was no way I was going to be able to manage a project with such whacky logic levels, like negative voltages for positive logic signals. I went down the TTL logic route for five years.

    This time, in 2018, I was determined to get further. I knew discrete component computers were built in the 50s and 60s, and I knew they were able to generate clock signals and have multi-phase clocks. All I had to do was find their schematics.

    So I did. I found a wealth of resources on the DEC PDP-8. It is a wonderful computer architecture. It has a single accumulator you use with something like 6502 zero-page memory addressing in order to perform calculations. It is very RISC-like with a tiny number of opcodes, and it only contains something like 500-odd gates. So in February I thought it would be a wonderful computer to clone.

    ...if only I had enough money.

    When I found out I could join this TTLers group, I decided I wanted to share my research on the strange DTL architecture of the PDP-8 in the hope it would help somebody.

    The Standard Logic Pulse of the PDP-8

    Before I start describing the electrical and logical system of the PDP-8, I want to explain how I came to obtain all this information. I retrieved it from Virtually the entire library of information required in order to repair, construct or just simply understand the PDP-8, as well as other DEC minicomputers, is all online at that website.

    All of the information I have explained here comes from the DEC 1967 Digital Logic Handbook. It is the last digital logic handbook that uses R-series logic. From 1968 onwards, DEC uses M-series logic, which is basically just normal TTL.

    Anyway here is the standard logic pulse of the PDP-8.

    The PDP-8 uses DEC's proprietary R-series logic. As the following diagrams explain, R-series logic takes a -3V signal to be a digital ONE,...

    Read more »

  • Dynamic RAM with single MOSFET per bit ?

    Yann Guidon / YGDES08/20/2016 at 22:54 28 comments

    RAM is one big problem for "discrete projects". It must be fast, large and cost-effective. There are many types of discrete RAM but none that is based on discrete MOSFET (yet).

    Integrated DRAM uses MOSFETs but they differ from the discrete form because of the intrinsic diode with the substrate : it takes two discrete MOSFET to make one normal MOSFET. This would not be cost-effective to use discrete MOSFET to implement classic DRAM circuits.

    I found inspiration with the diode-capacitor cell described for the TIM computers :

    Diode-capacitor dynamic memory

    I can't figure out what capacitance was used in the relay-based TIM8. However, with a MOSET-based circuit, the capacitance can be greatly reduced (to 100nF for example) because the required trigger energy is considerably lower. I even have a reel of dual Schottky diodes in SOT23. But I'm not sure about the leakage...

    Now, a good MOSFET has a pretty low leakage. I have played around (on paper) and have come up with a topology that replaces the diode with a MOSFET. The gate capacitance is not used but the parasitic diode is !

    Each access cycle takes 2 steps:

    • Read and empty the storage capacitor: drive RD high => This pushes the capacitor's lower electrode high, which is then read on the Data line. Probably a threshold current is required to read a "1".
    • Write the value: drive the desired level on the Data line, drive RD to 0V and WR to 1 (let the current flow to RD so the lower electrode is 0V).

    It's funny that the read phase works a bit like a charge pump...

    Data, RD and WR are totem-pole (complementary) drivers. I will have to try different circuits for the sense. The line and column select (demultiplexers) will need a lot of transistors too... But at least it's more compact than the only other MOSFET RAM that I know :-)

    Now I wonder what should be the refresh frequency...

    Any comment/remark/historical perspective ?

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Olivier Bailleux wrote 02/11/2018 at 08:39 point

Do you know the ?

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Yann Guidon / YGDES wrote 02/13/2018 at 05:40 point

who doesn't ? :-)

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Dylan Brophy wrote 02/13/2018 at 06:15 point

true :-D

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Yann Guidon / YGDES wrote 02/13/2018 at 16:10 point

Actually, it is listed, but with the old address. I'm updating the details page now.

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Frank Buss wrote 11/06/2017 at 00:01 point

I designed a simple CPU some years ago, optimized for running Forth:
The prototype worked in a FPGA.

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Yann Guidon / YGDES wrote 11/06/2017 at 00:14 point

you cheated then ;-) what keeps you from building it out of discrete transistors like the #AYTABTU - Discrete Computer  or #ED-64: A discrete 8-bit computer ? :-P

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Frank Buss wrote 11/06/2017 at 00:43 point

I guess I could do this, but this would be another week long project, and I have already so many unfinished projects :-)

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tomtibbetts wrote 11/05/2017 at 21:54 point

Hi, maybe this is not the correct forum.  But I have an issue with ringing on clock pulses.  I am building a SAP 1 computer on PCBs ( and the clock circuit is producing clock pulses that sometimes have a bit of ringing on both the rising and trailing edges of the pulse.  it doesn't happen all the time but there does seem to be a pattern to it.  One of the clocks is used for the sequencer and the other is for clocking all the registers.  Because of the ringing, the counters sometimes get double clocked and will skip a count.  What would be causing this?  Any help is appreciated.  Thanks

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Yann Guidon / YGDES wrote 11/05/2017 at 22:55 point

It would be a good idea to detail everything in a log (or more) on the project's page, because so far, the only answer I can give is to try to add a series resistance, add a 100ohms adjustable in series and check the bounces with a scope to see which impedance matches your tracks ?
Also : make sure you have a balanced and clean clock tree to prevent crazy matching problems.

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Marcel van Kervinck wrote 11/06/2017 at 12:15 point

I found this document helpful, specifically figure 17.

For my computers I found there is some more ringing with FETs (74HCT) than with bipolars (74LS). But it never caused misbehaviour and I see no clipping, so I'm still with architecture (a) on my boards. I was prepared to add series resistors (option c) as a possible counter measure.

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Yann Guidon / YGDES wrote 09/23/2017 at 13:53 point

@256byteram , @Peter Bosch , @Tony Robinson  and @John Croudy  are still invited to the project :-)

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Yann Guidon / YGDES wrote 09/23/2017 at 02:38 point

Oh I missed that one :-D

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Bill Rowe wrote 07/11/2017 at 20:23 point

Hi: Is there such a thing as a practical logic minimizer?  Something where you would feed in a truth table with N inputs and M outputs and get out a configuration of 7400/4000 chips that would implement it?

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BigEd wrote 07/11/2017 at 20:28 point

Maybe Project Icestorm would do it? I know that with Xilinx' tools it's possible to get a logic netlist - not 7400, but logic gates. See

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jaromir.sukuba wrote 07/12/2017 at 08:24 point

Take a look at Logic Friday -

You enter logic table, software spits out schematics made of logic gates of your choice. I used that thing when designing my #Fourbit

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Dr. Cockroach wrote 07/12/2017 at 08:51 point

Thanks Jaromir for the link to Logic Friday, looks like a tool I can use for my project :-)

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Bill Rowe wrote 07/12/2017 at 10:51 point

Excellent - thanks.  I'll have a look.

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agp.cooper wrote 09/23/2017 at 06:48 point

I use Logic Friday. It is a GUI for Expresso. It has a 16 input/output limit so beyond that you need to go directly to Expresso (I use a bat/cmd file). It optimises for generic gates packages or die-area.

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Yann Guidon / YGDES wrote 01/11/2017 at 21:00 point

The list is growing. It feels good to be surrounded by so many ace designers !

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Yann Guidon / YGDES wrote 03/25/2016 at 23:06 point

Wow we are already 11 TTLers ! 3 have not yet accepted the invitation though.

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Dr. Cockroach wrote 12/22/2016 at 22:28 point

Thank you for the invite, I'm in :-)

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