MIKBUG on Multicomp

Get MIKBUG on running on Multicomp

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Grant Searle's Multicomp has ROM images for Z80 (CP/M and BASIC), 6502 (BASIC) and 6809 (BASIC) CPUs. Grant also has support for the 6800 but doesn't have a standard software image to run. Source code for the classic MIKBUG exists and makes a nice early retro computer.

MIKBUG was the classic Motorola ROM for the MC6800 CPU.  Engineering Note 100 has the original source code. The downside of the original code is that it used bit-banging of a Parallel port for serial I/O. 

There is some recent work on MIKBUG.

Mike Lee has a MC6802 build which  has a MC6850 ACIA (UART) instead of the parallel I/O port. This fits nicely with Multicomp which provides two versions of the ACIA. One of the versions is brought to a serial port. The other implements the UART as a VGA output with PS/2 keyboard. This allows the FPGA card to emulate an external terminal without extra hardware.

We've done several builds of FPGA cards with support for a VGA monitor and PS/2 keyboard. Our most recent build, the RETRO-EP4CE15 uses an Intel/Altera EP4CE15 FPGA. This FPGA has enough internal SRAM to provide the 32K of SRAM plus store the MIKBUG ROM contents.

Mike Lee's board has the following hardware:

  • MC6802 CPU
  • SRAM at $0000-$7FFF (32KB)
  • EPROM at $F000-$FFFF (16KB)
  • (2) MC6821 Dual 8-bit Parallel I/O devices for 32 bits of I/O at $8000/1 and $8008/9
  • MC6850 ACIA at $8018/9

MIKBUG is fairly small and only uses space from $C000-$C8FF . I wonder if the end address might be a typo? Perhaps it is actually $C000-$C8FF. The "Operating System" scratch space is at $7F00-$7FFF so there will need to be RAM at the top of the 32KB SRAM range - should be no problem for the EP4CE15 FPGA.

The address decoding is trivial.

Mike has source code for the SMITHBUGS version of MIKBUG which uses the ACIA for I/O. The code has defines for the PIA but doesn't have any initialization code so it should be possible to build the FPGA without including PIA hardware.

  • Running on "original" Multicomp Hardware

    land-boards.com04/04/2020 at 15:52 0 comments

    Got MIKBUG up and running on the EP2C5-DB card which implements Grant's original Multicomp hardware design (defines which pins of the FPGA go to which I/O in a "standardized" way).  The GitHub code is here.  Running with external SRAM (32KB used out of the 128KB SRAM part). 

    A jumper on J8 provides port selection between the Serial port (on J5) and the VDU (VGA output and PS/2 input). Installing the jumper to the adjacent ground pin routes I/O to the Serial port. Removing the jumper routes I/O to the VDU. In the picture below the Serial port is wired to an external FTDI card.

  • Running on Rev 2 FPGA card

    land-boards.com03/08/2020 at 11:09 0 comments

    Built up a rev 2 RETRO-EP4CE15 card. The Rev 2 card replaces the USB C connector with a USB Micro connector. It also changes the VGA HD15 connector to the more usual footprint.

    Re-compiled all of the Multicomp examples and got them working (GitHub repositories). Also, got my 32-bit RISC CPU (R32V2020) running.

  • Demo Video

    land-boards.com03/06/2020 at 14:15 0 comments

  • Ported to Second FPGA Card

    land-boards.com03/06/2020 at 02:02 0 comments

    Ported the design to another FPGA card, the RETRO-EP4 card.

    This card uses a smaller FPGA, the Altera/Intel EP4CE6. This FPGA has less resources than the EP4CE15 card. Both have more than enough logic cells to implement the CPU and other logic, but the EP4CE6 FPGA has less Block RAM. To make this fit the SRAM was reduced from 32KB to 16KB. 

    The features are:


    ; Fitter Summary                                                                   ;
    ; Fitter Status                      ; Successful - Thu Mar 05 20:49:24 2020       ;
    ; Quartus Prime Version              ; 18.1.0 Build 625 09/12/2018 SJ Lite Edition ;
    ; Revision Name                      ; M6800_MIKBUG                                ;
    ; Top-level Entity Name              ; M6800_MIKBUG                                ;
    ; Family                             ; Cyclone IV E                                ;
    ; Device                             ; EP4CE6E22C8                                 ;
    ; Timing Models                      ; Final                                       ;
    ; Total logic elements               ; 2,940 / 6,272 ( 47 % )                      ;
    ;     Total combinational functions  ; 2,827 / 6,272 ( 45 % )                      ;
    ;     Dedicated logic registers      ; 802 / 6,272 ( 13 % )                        ;
    ; Total registers                    ; 802                                         ;
    ; Total pins                         ; 47 / 92 ( 51 % )                            ;
    ; Total virtual pins                 ; 0                                           ;
    ; Total memory bits                  ; 221,312 / 276,480 ( 80 % )                  ;
    ; Embedded Multiplier 9-bit elements ; 0 / 30 ( 0 % )                              ;
    ; Total PLLs                         ; 0 / 2 ( 0 % )                               ;

     The Memory Blocks were:

    ; M9Ks                                        ; 28 / 30 ( 93 % )           ;
    ; Total block memory bits                     ; 221,312 / 276,480 ( 80 % ) ;
    ; Total block memory implementation bits      ; 258,048 / 276,480 ( 93 % ) ;

  • Write Cycle Timing

    land-boards.com03/04/2020 at 17:59 0 comments

    One of the nicer things about the 6800 FPGA core is that it doesn't need a dual phase clock. However, the operation of the clock is not particularly well documented for the FPGA core. At the very least there's no comments in the code that explain the clock operation. To get an idea what is going on we will have to take a look at the VHDL code. The typical use in the VHDL code for the cpu68 core looks like this:

    if clk'event and clk = '0' then

    This usage leads me to think that the falling edge is the start of the cycle. All uses of the clock follow the same falling edge style. This makes me conclude that the clock is the equivalent of the Phase 2 clock from the data sheet.

    The equations for the active low write strobe that seem to work are like this:

    n_WR => n_if1CS or w_R1W0  or (not w_vma) or (not w_cpuClock),

    The sense of this equation feels backwards at first but basically if read in the negative it says something like:

    De-assert write strobe when not chip select OR when read OR when not VMA or when not clock.

    Flipping this around - assert write when chip select AND write AND VME and CPU Clock. That also corresponds to the Phase 2 clock high.

    If anyone has better knowledge, feel free to comment.

    This is in contrast to the MC6502 CPU (T65) core which is rising edge driven so any example VHDL code for the 6502 will need to use the other edge.

    Double Strobes

    I've seen some effects which seem like double strobes when I've messed around with these signals. This is particularly a problem when the CPU speed is increased. The CPU may be too fast, but the Buffered UART and VDU interfaces work with other faster Multicomp designs so I'm skeptical that is the issue. Grant didn't publish a 6800 reference design so we are somewhat on our own here.

  • Add ACIA (Serial) Port

    land-boards.com03/04/2020 at 15:39 0 comments

    There is currently an ACIA emulator which uses the ANSI Display and PS/2 keyboard connection. Adding a second ACIA port which will use I/O pins as a serial port. An FTDI can be attached to these pins which will allow access from a Computer USB port. This is easier for screen capture and uploading of S-Record files.

    Using Neal Crook's "Buffered UART" VHDL code which has improvements compared with Grant's ACIA code but it has a small difference since it uses Serial Clock Enables.

    Locating the new serial port at addresses $8028-$8029.

    Adding a serial port select jumper using one of the J3 jumper blocks on the RETRO-EP4CE15 card. If the jumper is left out the VDU and PS/2 are used for I/O. If the jumper is installed the new serial port is used for I/O. This is done by swapping the memory decode addresses.

    Tested and works.

  • Writing a Program

    land-boards.com03/02/2020 at 12:03 0 comments

    Now that the toolchain works, it is possible to write a program, assemble the program, enter the program in RAM, and then run the program.

    The Assembler

    The a68 Assembler is here. The MIKBUG debugger source file is here

    Typing in a short program

    Typing in a program is time consuming, There are standard entry points for the debugger I/O which can be called. The list file for the debugger is here.

    A simple program example is to read a character from the PS/2 keyboard and then write it out to the Video Display Unit (VDU).

    The function to input a character from the PS/2 keyboard is:

                            ;    INPUT ONE CHAR INTO A-REGISTER
       c1f3   8d fa         INEEE     BSR    SAV
       c1f5   b6 80 18      IN1    LDAA    ACIACS
       c1f8   47                ASRA
       c1f9   24 fa             BCC    IN1     ;RECEIVE NOT READY
       c1fb   b6 80 19          LDAA   ACIADA  ;INPUT CHARACTER
       c1fe   84 7f             ANDA   #$7F    ;RESET PARITY BIT
       c200   81 7f             CMPA   #$7F
       c202   27 f1             BEQ    IN1     ;IF RUBOUT, GET NEXT CHAR
       c204   7d 7f 0d          TST    ECHO
       c207   2f 01             BLE    OUTEEE
       c209   39                RTS

    The function to output a character to the VDU is:

                            ;    OUTPUT ONE CHAR 
       c20a   36            OUTEEE    PSH    A
       c20b   b6 80 18      OUTEEE1 LDA A    ACIACS
       c20e   47                ASR A
       c20f   47                ASR A
       c210   24 f9             BCC OUTEEE1
       c212   32                PUL A
       c213   b7 80 19          STA A ACIADA
       c216   39                RTS

    It should be easy to write the code to read a character and then echo it out. Here is the instruction set card for the 6800. The In/out functions are written as subroutines can get called with a JSR. The instruction to jump to a subroutine is:

    The instruction to branch back to start is:

    The code to do this should look something like the following:
    ; INEEE    EQU    $C1F4
    ; OUTEEE   EQU    $C20A
        JSR    $C1F4
        JSR    $C20A
        BRA    LOOP4VR

    The listing file is:

       0000                 LOOP4VR
       0000   bd c1 f4          JSR $C1F4
       0003   bd c2 0a          JSR    $C20A
       0006   20 f8             BRA    LOOP4VR

     Commands to enter, disassemble and run program:


     Runs but prints a lot of chars...

  • MIKBUG Commands

    land-boards.com03/01/2020 at 20:55 0 comments

    MIKBUG (Smithbug) has the following case-sensitive commands.

    ; F FIND 



    ; R PRINT

    ; O ECHO ON
    ; N ECHO OFF

    View Memory

    >V FROM ADDR 0000 0000 20 61 01 C3  4A 49 1E 2D  32 D0 3F 7A  D4 E3 E1 0F      ...JI.-2.?..... 0010 C0 2E D2 08  83 69 11 80  0B AC 43 A2  C2 28 B1 BD     ..........C..(.. 0020 F1 96 68 69  65 20 D4 C2  92 DE 5C 8F  61 22 08 74     ..... ....\..".. 0030 21 11 67 7A  AF 47 18 51  EE A3 10 80  46 61 45 89     !....G.Q....F.E. 0040 C2 89 D6 A8  E8 21 8E 0A  92 E2 07 48  67 E4 4D CA     .....!.....H..M. 0050 5E 00 88 17  B1 C2 D2 2A  E3 46 F3 40  10 7D 00 EF     ^......*.F.@.... 0060 A2 04 58 91  8C E3 90 28  01 9C E1 36  F8 80 48 C2     ..X....(...6..H. 0070 BB 04 B8 59  9B C5 82 8D  46 F0 28 DB  06 4D 69 84     ...Y....F.(..M..

     Change Memory

    >E 0000
    >0000 20
    >0001 61
    >0002 01
    >0003 C3
    >0004 4A
    >0005 49
    >0006 1E
    >0007 2D
    >0008 32
    >0009 D0
    >000A 3F
    >000B 7A

    Disassemble Code from Memory

    FROM ADDR D000
    D000 8E LDS   #$7F44     ..D
    D003 BF STS   $7F0A      ...
    D006 7F CLR   $7F0D      ...
    D009 CE LDX   #$C125     ..%
    D00C FF STX   $7F17      ...
    D00F FF STX   $7F08      ...
    D012 86 LDA A #$03        ..
    D014 B7 STA A $8018      ...
    D017 01 NOP                .
    D018 01 NOP                .
    D019 01 NOP                .
    D01A 86 LDA A #$15        ..
    D01C B7 STA A $7F0C      ...
    D01F B6 LDA A $7F0C      ...
    D022 B7 STA A $8018      ...
    D025 8E LDS   #$7F44     ..D
    D028 8E LDS   #$7F62     ...
    D02B 7F CLR   $7F13      ...
    D02E 7F CLR   $7F16      ...
    D031 7F CLR   $7F6D      ...
    D034 CE LDX   #$C76B     ...
    D037 8D BSR   $61   D09A  ..
    D039 8D BSR   $59   D094  .Y
    D03B 16 TAB                .
    D03C BD JSR   $C0EF      ...

  • Code Running!

    land-boards.com03/01/2020 at 20:53 0 comments

    It runs. Here's the disassemble command:

    Here's the dump memory command:

  • VHDL Changes

    land-boards.com03/01/2020 at 20:42 0 comments

    Did quite a few changes to the VHDL code. Here it is in GitHub.

    • Added vma (Valid memory address) signal into write strobes
    • Made CPU clock run at 1 MHz (will probably run faster)
    • Removed ACIA code - just using VDU with 6850 interface
    • Moved ACIA base address to $8018-$C8019 (Matches Smithbug v2)
    • Gating clock (not) into write strobes
    • Re-named signal names generally per Nandland signal naming conventions 
    • Left External SRAM and SDRAM interfaces but drove to inactive levels
    • 4KB of EPROM with 4X "copies"
    • 32KB of SRAM
    • Fits into FPGA with room to spare

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