Herring is designed as a passive backplane system. The backplane PCB provides DC input, a 5v regulator, a reset button and the system bus. Everything else is done on the individual boards.
Fits a 6502 (or pin-compatible) CPU. Connects address and data buses as well as most of the CPU control lines directly to the system bus.
Each memory board holds a single 8KB or 32KB ROM or RAM chip. The size is configurable with onboard jumpers. Multiple boards can be installed to allow different memory configurations. The base system is designed with a single 8KB ROM and 32KB RAM board installed.
A 6522 VIA chip is used to provide 16 GPIO lines. These I/O pins are exposed on two 2x7 box headers, allowing jumper wire or ribbon cable connections to peripherals. Currently, there is an LED board which connects each I/O pin to its own LED.
A 6551 ACIA creates a simple UART for the system. This serial port can run at up to 19200 baud. An onboard 1.8432 MHz crystal provides the ACIA with a clock for its internal baudrate generation.
This board provides a system clock in the form of an oscillator and address decoding / glue logic with a ATF16V8B GAL chip. The GAL takes in address and control lines from the system bus and outputs eight "decoder" lines that can be used as chip-select pins for various peripherals.
System Bus Pins
This pin layout is valid for v1.4. Slight changes will be made in v1.5.
The system bus consists of a single 40 pin header. The pins are in order as follows:
1. VCC - 5v regulated input
2. GND - ground connection
3-10. Data pin 0 through data pin 7
11-26. Address pin 0 through address pin 15
27. RES - system reset pin (active low)
28. CLK_OUT - system clock after passing through the CPU (i.e. PHI20 on the 6502)
29. RW - read/write pin on the 6502
30. IRQ - interrupt request
31-38. Decoder 0 through decoder 7, used for peripheral chip-select
39. CLK_IN - system clock input from an oscillator or other source
40. GND - ground connection