Network Usage Meter

A real time display of current network usage. Data displayed on LED matrix and sent over serial UART to host for plotting.

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As a geek, I like to know my network utlization when I'm gaming/streaming/bored (okay, all the time!). I wanted a device that would sit between my router and cable modem and provide download rates (Mbps) in real time. I wanted to create a standalone device that could be plugged into any 10/100Base-T network and work without any user configuration or complicated installation. I also wanted my device to not interrupt normal network operations. Thus the network usage monitor was born! The monitor consists of four main components: a PIC24F microcontroller, a passive network tap, an ENC624J600 MAC/PHY chip and a pair of 8x8 LED matrices. The MAC/PHY chip is configured to operate in "promiscuous mode", storing all network data in a buffer. The microcontroller continually empties the buffer and records how much data was emptied. Once per second, the total amount of data read from the buffer displayed on the LED matrices and is also sent via UART to a host for plotting.

The PIC microcontroller communicates with a MAC/PHY chip to receive network traffic. The PIC keeps track of the total amount of data that is received per second. Then, once per second the data is sent to two interfaces, a serial UART to a host device and onto a LED matrix. The LED matrix displays the last 16 (8x2) seconds of network usage data.

The system diagram below illustrates how the monitor connects to an existing network using a passive tap.

Bandwidht Monitor System Diagram

The plot below is compares the serial output (plotted in python) from the network monitor (left) against a DD-WRT plot (right).

The eagle schematic illustrates how the PIC interfaces with the MAC/PHY chip via a parallel port and to the LED matrix via a SPI interface. The eagle pcb layout has headers for power, a programmer, MAC/PHY, UART and SPI.

Eagle Schematic v1.2

Eagle PCB v1.2

Source Files 

Unless otherwise specified, all posted code and designs are available under the MIT license.

Eagle schematic

Eagle PCB layout

PIC source code

Plotting Software

Laser Cut Case

  • 1 × PIC24FJ128GA310 Microprocessors, Microcontrollers, DSPs / Microcontrollers (MCUs)
  • 1 × ENC624J600 Interface and IO ICs / Ethernet, T1, E1
  • 1 × Throwing Star LAN Tap Passive Network Tap
  • 2 × 8x8 LED Matrix Blinky things
  • 2 × MAX7219 Interface and IO ICs / Display Interface

  • LED Matrix + Laser Cut Case

    bonafidegeek08/13/2014 at 01:20 0 comments

    I purchased a couple of 8x8 LED matrices. The LEDs are controlled by a MAX7219 chip with a SPI interface. In the video below you can see the results. I chained two matrices together to form a 8 x 16 grid. The vertical direction represents the download rate for a one seconds. The scale is roughly adjusted such that a full vertical bar corresponds to the maximum download rate on my network. I plan on getting another set of LED matrices of a different color to display the upload rates.

    I designed a front plate and back plate and had them laser cut out of 3mm clear acrylic. I didn't have any standoffs on hand, so I made some out of cut down pens and zip ties.

  • Plotting with Python

    bonafidegeek08/13/2014 at 01:19 0 comments

    With v1.1 populated, I was able to interface with the MAC+PHY chip via the parallel interface and begin sending download rate data over the serial port. I wrote a Python program to plot the data, and compared it with the bandwidth graphs provided by DD-WRT on the router. To my delight, the plots track pretty closely.

    Python plot of live data from in-line bandwidth meter vs DD-WRT plotPython + in-line bandwidth meter vs. DD-WRT

  • Microcontroller Hunt

    bonafidegeek08/13/2014 at 01:18 0 comments

    I began searching for a microprocessor with a parallel interface with sufficient data rates for my needs. I found the PIC24F to be a suitable candidate and began laying out a pcb to interface with ENC624J600 breakout board I purchased.

    PCB v1.0 back from fab

    PCB v1.1 back from fab

    PCB v1.2 back from fab

    In-line bandwidth meter v1.1 mockup

  • Passive Network Tap

    bonafidegeek08/13/2014 at 01:16 0 comments

    I created a prototype passive network tap out of female RJ-45 push down sockets. Under normal conditions, data is transmitted on TX and recieved on RX, however when sniffing traffic on a line, the listening device must treat each direction as seperate receive channels. To handle two RX channels, two NICs are required.

    10/100Base-T Passive Network Tap

    I ran into Mike Ossman at a GNU Radio conference and received one of his Throwing Star LAN Tap. He uses them as business cards, how cool is that? If I ever get around to populating the board, it will certainly clean up my protyping efforts a bit.

    MAC + PHY chip

    The bandwidth meter operates at the ethernet frame level, counting bytes transmitted and received (including headers). As such, I looked for a MAC + PHY chip with a large receive buffer and the ability to handle raw ethernet frames. I first looked at the

    WIZnet module, but found it's raw ethernet support lacking. The interface could only store one raw ethernet frame at a time and block any incoming packets until the first frame is read. For this application, the blocked packets would lead to an incorrect byte count and defeat the purpose of the meter.

    I ultimately selected the ENC624J600 chip.

    Unlike the WIZnet module, the ENC624J600 does not have a built in TCP/IP stack, but had a much better raw ethernet interface. I ordered a single

    Olimex breakout module from Mouser to get going. I planned on making a PCB with two ENC624J600 chips and some flavor of Atmel to keep track of the packet count and drive the display. The SPI IO pins on the ENC624J600 are 5v tolerant and the Atmega128 recognized ~3.3v as high, so the level shifters weren't needed.

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