• Construction

    Keith05/28/2023 at 00:28 0 comments

    My initial placement. I have the 32K RAM chips under the ROM sockets. This simplifies wiring a lot. They are directly soldered to the PCB, because they won't be changed and they are nowadays cheap enough to not bother recovering.

    On the right is a simple board I use to take 5V from a common wall-wart power supply with 2.1mm inner pin, and apply it to the STEbus power pins. There is also a 5V to 12-0-12 volt DCDC converter, which drives the +/- 12V rails.

    An early shot of the underside, before the bus signal wires were fitted. I use surface mount decoupling capacitors because they were easy to fit and take little board area.

    Note that most small DCDC converters have poor regulation. They are probably as sophisticated as a 555 oscillator driving a small transformer and a rectifier. Yes they may give the nominal voltage at the working load, but the data sheet graphs usually show the voltage goes up at lighter loads. This may well be above the absolute maximum rating of the chips they drive. Some kind of upper voltage limiting is advisable.

    Also note that they are not very tough. Accidentally putting an RS232 buffer in the wrong way round can overload and destroy small converters, as I found by experience. Order a spare, to be prepared.

  • Clock stretching

    Keith05/27/2022 at 22:29 4 comments

    There were no STEbus 6502 designs to reverse engineer so I've had to tackle this one from scratch.

    Essentially we need to make the synchronous 6502 look more like an asynchronous 68008.

    The STEbus data strobe signal (DATSTB*) is asserted (low) when all the address and data lines are valid. There is a 40 ns setup time requirement.

    The 6502 clock out signal (E) is asserted (high) when all the address and data lines are valid.

    So E can drive DATSTB* through a 40 ns delay and an inverting gate. However, E must not go low until the STEbus slave returns a DATACK* signal. 

    Let us begin by considering an oscillator running at twice the 6502 clock rate, driving a simple 74LS74 D-type latch with the D input fed by the /Q output. The Q output will toggle at the 6502 clock rate.

    Now we can stretch the clock by adding a delay between the /Q and D pins. A shift register will do the job. With the proviso that it will need clearing to all zeros (or all ones) regularly to avoid invalid states.  The STEbus prototyping board uses an 8-bit shift register with clear, the 74LS164, for cycle stretching. Read the timing explanation to see how it works.

    The shift register outputs look like this:

    00000000 when E is low, all cleared.
    10000000 when E is high, starts entering shift register

    You can feed any shifted signal, a to d, inverted back to the D input of the 74LS74 flip flop, and stretch the E high time.

    The E low time is not stretched. Yes, that does mean the high and low times are going to be different. That is going to look weird to people used to conventional 6502 designs. But it is completely legitimate. They can't touch you for it! You can have any duty cycle you want, though of course it has to be 50:50 at the maximum clock rate.

    The E low time will be the minimum for all access cycles. There is no reason why it should not, because the 6502 bus lines are invalid and no other device can do anything. All the 6502 is doing is internal stuff, and it can do that at top speed.

    In a realistic system you will have various devices of various speeds. The devices are memory mapped, so the delay has to be selected by the address lines.

    As a simple example demonstration of how to do this, consider a 1-of-8 multiplexer between the shift register taps and the inverter feeding the D input of the 74LS74 flip flop. Address lines A15-13 select the shift register output for each of eight 8K spaces. Each 8K space can have a different E high time, or the same, depending on how you wire it.

    In practice, memory maps are not so simple and my prototype design uses GAL chips to select the delay. It makes sense to have the delay-selection in the same logic chip as the device-selection.

    In my design, there are different fixed delays for ROM (fairly fast), RAM (very fast) and I/O (USB module). For STEbus access, the DATACK* signal is sensed, allowing for a variable delay. 

    I have also compromised on the clock speed. The STEbus requires a 16 MHz timing clock, while the 65C02 is rated at 14 MHz. I am running my 65C02 at 8 MHz because this is easily derived from the 16 MHz oscillator and 16 MHz would be overclocking the 65C02. That is something I would try when I have  a printed circuit board but not with vero-wire on protoboard.