Boots from a 55ns Flash ROM, copies the BIOS and 16K BBC BASIC into the shadow RAM, then disables the ROM.
RAM is two 15ns 32K RAM chips, cache-RAM chips from old PCs.
It uses a novel asymmetric clock stretching circuit to access different devices at different speeds, on a cycle-by-cycle basis. When it accesses the STEbus, PHI2 high time can last indefinitely.
USB module is a fast replacement for RS232. Control bits were mapped to look like an Acorn Tube ULA, so I could use the firmware from a BBC micro second processor. Boot ROM includes BBC BASIC. This runs very fast through the USB link. Currently running at 8MHz, aiming for 16.
Prototype only does I/O cycles for now, but this is enough to prove the glue-logic concepts. Next stage is to move glue logic from two GALS to one CPLD. I prefer Xilinx but they are abandoning 5V versions. I can either change to all-3V onboard or use an Altera CPLD.
32K SRAM, 0.3" wide, 15 to 25 ns access
Lower RAM and Upper RAM (boot ROM is copied to upper RAM)