DIY System on Chip based on FPGA, priced below 5 USD

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NOTE all production documentation and source code in main github repo.

DIY Yourself System On Chip, at below 5 USD pricing, hacking friendly, small and low power.

Sized 10x10mm, priced sub 5 USD (BOM price approx 1.5 USD) FPGA Module with ultra low power consumption. Easy accessible 100mil pin header style design.

Can be used "custom IC" when the FPGA OTP internal NV memory is burned or as coprocessor or accelerator for slow microcontrollers configured over SPI interface.


You might have hit that point when your microcontroller peripheral just doesn't have exactly the features you need:

Dipsy comes to the rescue!

It's a tiny FPGA (Lattice iCE40UL1K-SWG16) on a tiny 10 x 10 mm², breadboard-friendly PCB:

With 1284 logic cells, 7 kB RAM and a few extra goodies in this tiny package, it's the perfect addition to your already breadboarded prototype, and it can also be integrated into a pcb using simple pin headers.

Learn FPGA basics with dipsy!

Learn Verilog or VHDL with dipsy. Large FPGAs can be quite daunting, like this thing:

(picture: Keld Gydum,, picasa link)

and usually come in huge packages you don't really want. Dipsy is more like:

You'll quickly know your way around and the probability of meeting someone you don't even know is significantly lower.

What do I get with dipsy?

Apart from 1284 logic cells and 7 kB RAM you'll get

  • Two built-in I2C interfaces
  • a 48 MHz oscillator
  • a 10 kHz oscillator
  • IR TX/RX
  • 3x 24 mA, 1x 100 mA, 1x 400 mA LED driver
  • up to 10 I/O
  • on-board core voltage regulator

What can it do for me?

It's the perfect addition to your project when you don't want that huge FPGA, probably in a QFP144 package, with a million logic tiles when everything you need is a custom device with a few PWM channels or something similarly simple:

  • Like a servo controller.
  • Or a WS2812 frame buffer.
  • Or a device that maps your monochrome pixel data to something your color display can understand
  • Or a fast data aquisition device with a small buffer
  • Or a simple AVR core (yes, that does fit indeed!)

How do I develop software for it?

Compile your mixed Verilog/VHDL design with Lattice's iCECube 2 software. If you want you can also use other software (like Xilinx's Vivado) to develop and simulate you code first:

Do I need anything special to program it?

Absolutely not! A binary configuration for dipsy is less than 32 kB in size, so you can include it in your arduino sketch, or store it in an external EEPROM or SD card if your microcontroller doesn't have the extra flash space. dipsy can be configured with a simple SPI interface, and we even have an arduino library for that!

What if I don't use arduino?

No problem, it's easy enough to port to other environments and languages. We have tested dipsy with

  • Raspberry Pi,
  • BeagleBone Black
  • Intel Edison
  • Teensy 3.1 and LC

We're also working on a tool to program dipsy with USB<->Serial bridges.

The configuration is stored in

  • volatile internal configuration memory,
  • one-time programmable configuration memory,
  • or an external config flash chip
The first option is easiest for prototyping SPI slaves, and we currently recommend that - it's also what our arduino library does.

See a WS2812B test in action:

We also have very basic examples, starting with the classic blinky, to get you started with this FPGA board!

Five grains of Sand

All components (FPGA, voltage regulator and three passives) on the dipsy PCB are smaller than 2mm. We give you those five grains of sand to

  • Invent a new Processor Architecture and Instruction Set
  • Design a System On Chip based on the architecture you invented
  • Create a Computer or embedded system based on the SoC you designed
  • Or just design a custom peripheral for your existing project

Take the task!

Do it


Bill of Materials

  • Lattice iCE40UL1K-SWG16
  • TLP713 LDO
  • 2x Capacitor 1 µF 0402
  • Resistor 10 K 0402
This is all you need to build a custom System on Chip, all you need are 5 grains of Sand.

System Diagram


  • Hardware design (Schematic, PCB, Production files)

The hardware license is the most important one, there are many tools and utilities and IP Cores that may have different or undefined unknown license. It is not possible to document all those use cases.

As example, the set of tools that makes the open-source FPGA toolchain is a mix of MIT, GPL, Public Domain and "missing" licenses.

AVR Basic Compiler - is fully copyrighted by Antti Lukats, but has been released under several different Company names in the past, and possible will be released under some new...

Read more »

  • 1 × PCB 10 x 10 mm!
  • 1 × Lattice iCE40UL1K-SWG16 Lattice ICE Ultralite FPGA
  • 1 × TLV713P Texas Instruments LDO 1.2V, ultra small package 1x1 mm chip size
  • 2 × 0402 Capacitor 1 uF
  • 1 × 0402 Resistor 10K

  • Refunds for indieGOGO

    Antti Lukats11/19/2017 at 17:48 1 comment

    Taking years go get myself together and refund the iGOGO project supporters. I should have done this ages ago, I know. The money was collected to company account - I would refund from my household money. Sorry folks.

  • DIPSY in Tokio, Japan

    Andrei Errapart10/04/2015 at 13:43 0 comments

    DIPSY has successfully landed in Japan and is right now watching the N700 Shinkansen passing by. Our apartment is in nearby Yokohama, thus we ourselves don't have to travel neither fast nor far.

  • Even Smaller!

    Antti Lukats10/01/2015 at 17:44 5 comments

    Measurements in millimeters!

    1. WS2812B compatible footprint
    3. 256KByte SPI Flash with multiboot option
    4. 2x LDO (Core and VIO)
    5. One use LED

  • SD Card emulation, first success

    Antti Lukats09/28/2015 at 18:37 1 comment

    Using DIPSY-EPT Emulator Programmer, but the HDL code should equally well work on DIPSY too. Just got the basic SD card working, Windows does show that there is new drive with README.TXT on it..

    There is still nice piece of work to optimize the HDL code to be bit smaller and then need add functions to REFLASH the SPI, and to issue WARM BOOT.

    Then a DIPSY with spi flash connected "as SD card" would be full self contained FPGA dev system, connect "AS sd card" reflash the second image, and "restart hardware with new hard app" !

    CMD55 and response seen in LA, while README.txt is read out from ICE FPGA BLOCK RAM..


    Antti Lukats09/26/2015 at 13:14 1 comment

    It's saturday, I am on the way to ONION-Market with my son Andre. Hey lets go via the office, maybe I can draw some PCB there? OK!

    I had the schematic and PCB template halfway ready.

    I explaining my son, that MOST of the components are in the schematic, he looks a sec and says the capacitors are missing? Right there was no power supply cap in the schematic, I add two, and Andre finishes the PCB (routed 100% as per actual schematic).

    Done :) the routing can of course be optimized, but it is already functional as it is. Andre is 13, I must discuss with him more about the use of DIPSY in school, what they do there is so boring.

  • Stolen DIPSY's.

    Antti Lukats09/25/2015 at 17:43 11 comments

    I would like to write more and well more about the HaD meetup in Zurich, but: on my way back home in the german highspeed ttrain ICE, my backpack was stolen from the shelf about my head.

    I have still 3 DIPSY units on my desk, the remaing ones I had in the packpack. There was a lot in that backpack. Direct value between maybe bit above 3KEUR (maybe more).

    you can support DIPSY, if you can do so please.

    PS. DIPSY production units will be available in time before christmas, not exact ETA but they will be done with our real production machines and available in any quantity needed.

  • SD Card emulation & going ZURICH

    Antti Lukats09/23/2015 at 20:45 1 comment

    The SD card emulation IP Core, is not yet tested but at least compiled with ICEcube, and there are enough resources, so that is a good thing! Now just a bit time and it will work.

    heading out to zurich in 7 hours so see you there?


    Antti Lukats09/22/2015 at 20:24 6 comments

    This is really not that we should do in the kitchen, but if needed BGA's can be soldered easily with any heat source:

    The magic is really in the flux. Any other BGA is easier than this one, to get this right you really need to have alignment precison below 200 microns. The BGA will self align itself but this tiny thing still has to be placed very accuratly.

    We tried 3 times, first time the BGA was soldered perfectly but 180 degrees wrong, the second one was possible also perfect soldering, but I did drop it, and as it was still hot the BGA did come off.

    The 3r one I did bake too short, so it did not stick, so she had to place it 4th time, and well the solder was OK and the board actually works.

    All normal BGA packages are easy to handle - do not be afraid - 0.8 and 0.5 aligne itself much better than this small thingie..

  • Files commited to github

    Antti Lukats09/21/2015 at 20:34 0 comments

    more CAD sources, DIPSY spi tool software sources etc commited to main github repo.

  • DIPSY unboxing VIDEO

    Antti Lukats09/21/2015 at 19:35 5 comments

    I have received product samples and free development boards from Silicon Blue and from Lattice Semiconductor.

    Giving something back sounded like a good idea - so I sent DIPSY and DIPSY EPT (emulator programmer tool) to Lattice.

    As an hint from Hackaday team I did not include this video in the DIPSY best product finals video.

    But I like it anyway!

View all 58 project logs

Enjoy this project?



Jakub Biniek wrote 04/19/2018 at 19:12 point

Great work! Love it:) It is so tiny!

  Are you sure? yes | no

David wrote 09/29/2017 at 12:11 point

Can I buy one ? 

  Are you sure? yes | no

Patrick.pelgrims wrote 02/20/2017 at 17:07 point

Who was the PCB manufacturer ?

  Are you sure? yes | no

Paul Stoffregen wrote 02/19/2017 at 21:43 point

Antti, are assembled DIPSY boards selling anywhere?

  Are you sure? yes | no

donald murray wrote 11/19/2016 at 01:33 point

I really doubt that you are going to be able to fit an mcu in a thousand LCs. Might i suggest this product with 5K LEs for about $14..... is also easier to hook up to a breadboard, etc..,searchweb201602_5_10065_10068_10084_10083_10080_10082_10081_10060_10061_...

  Are you sure? yes | no

Ed S wrote 04/27/2016 at 13:41 point

Great looking project. Any update on how or when I can buy one or two?

  Are you sure? yes | no

Matt Palmer wrote 04/19/2016 at 12:50 point

I'm aching to buy and play with some of these...

  Are you sure? yes | no

Jonathan Chetwynd wrote 02/02/2016 at 16:24 point

is a new batch planned or available?


  Are you sure? yes | no

Patrick.pelgrims wrote 12/29/2015 at 15:18 point


Can you make the synthese results available for the avr in the smallest ice ?



  Are you sure? yes | no

s.tamasd wrote 11/07/2015 at 13:45 point

I just joined because of this project. How do I get one (or many) of these?

  Are you sure? yes | no

Yann Guidon / YGDES wrote 11/07/2015 at 13:59 point

Just like me :-)
Antti is extremely busy these days and I haven't received mine yet. Most of the DIPSies were stolen in a train, look at the log archives.
There was a campaign there but I suppose it will also appear there someday, when he runs a new batch.

  Are you sure? yes | no

Oscarv wrote 09/25/2015 at 20:14 point

Great meeting you in Zurich. So sorry to hear about your stolen backpack. Even though I am slightly desperate to get a Dispy, honestly: I did not do it! :) 

  Are you sure? yes | no

Dan Royer wrote 09/22/2015 at 22:36 point

How hard would it be to lay these in a grid for distributed computing?

  Are you sure? yes | no

Yann Guidon / YGDES wrote 09/23/2015 at 01:32 point

What do you have in mind ?

  Are you sure? yes | no

Dan Royer wrote 09/23/2015 at 01:52 point

distributed computing.  A lot of processing and not much ram spread over hundreds of nodes, rather than one massive CPU bottlenecking the pipeline.

  Are you sure? yes | no

Yann Guidon / YGDES wrote 09/23/2015 at 02:00 point

Well this depends very much on your problem but in all the cases, a single-chip, like a larger FPGA, is more efficient because communication is always what kills performance. I/O consume most of the power and decrease the actual bandwidth since computations take place so fast onchip.
You can put many tiny cores inside a decent FPGA that is cheaper than all the equivalent DIPSIES and it will be faster.
For an ASIC perspective, look at Chuck Moore's GreenArray :-)

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Antti Lukats wrote 09/23/2015 at 07:19 point

it is easy to arrange them in array so that all nodes can be recpnfgured with different hardware dynamically - sie of each "node" could be very small on PCB 2x2 mm per node :)

  Are you sure? yes | no

Juan Manuel Campos Olvera wrote 09/11/2015 at 19:55 point

I really want some of these 

  Are you sure? yes | no

Antti Lukats wrote 09/11/2015 at 20:02 point

we start shipping some next week, but we only have the "hand made ones" so not so many yet, full production coming up

  Are you sure? yes | no

Juan Manuel Campos Olvera wrote 09/11/2015 at 20:18 point

How do i order one?

  Are you sure? yes | no

Patrick.pelgrims wrote 08/12/2015 at 09:43 point

Dear Antti,

can we order already a few board to do some evaluation and tests ?

Did you the board in 75um track with ?



  Are you sure? yes | no

Antti Lukats wrote 08/12/2015 at 10:25 point

Hi I have as of today only 1 working unit I could send. PCBs and components we have more, but I am not sure when exactly and how many we will assemble.

  Are you sure? yes | no

Antti Lukats wrote 08/17/2015 at 19:19 point

We have some boards now, we test them and ship then

  Are you sure? yes | no

jaromir.sukuba wrote 08/30/2015 at 12:49 point

I'm definitely interested in getting one.

  Are you sure? yes | no

Antti Lukats wrote 07/14/2015 at 11:49 point

Hi we are in the process of defining the final pinout for DIPSY module, DIPSY addon and DIPSY socket, there are some consideration that made some small changes to the relative placement of some pins.

11AA160 - actually we would most likely use 11AA161 on the module, for 11AA160 to be used on customer PCB so the addresses do not collide

11AA160 is powered from 3.3V, 1.2V is only needed for ice core supply

  Are you sure? yes | no

Pete wrote 07/13/2015 at 21:52 point

The drawings here don't show the EEPROM you added yet, and I have a question about how you power it:  The 11AA160 is a 1.8v to 5.5v part, if I'm reading the specs right.  Is the TLV713P a fixed 1.2v output, or should that be 1.8v in the component list above?  

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Andrei Errapart wrote 07/10/2015 at 15:45 point

One could use a matrix of Dipsy-s fitted with RGB leds to implement a colourful version of Conway's Game of Life ( I think it woudl be cool to fit DIPSY with an SPDIF receiver combined with digital signal filters in order to drive RGB leds on a Christmas tree to the rhytm of music.

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Antti Lukats wrote 07/04/2015 at 17:12 point

I am trying to answer: I used heavily modified core originating from jesus@opencores, I think he was an swedish guy who disappeared from public long time ago. I did modify the instruction set a bit, to implement FAST input output. This modified core was used in some real products also, one such use was in Actel A3P60, where I implemented "paging", so the AVR had one fixed and one page for "dynamic overlay", if execution had to jump to page not currently loaded, it did special jump to first address of the dynapage, with reference to absolute address in SPI flash. This jump caused the page to be pre-loaded. This product was selling in 100K+ qty ASFAIK, maybe more as it got cloned in china.

Executing directly from SPI is also possible, but I have not made such version, yet. I have been playing long time with an idea of soft core that is optimized for direct execution from serial media, some research and pre-work done, but no promises of any kind.

But in any case, 1280 LUT + 14 Block RAM's is enough for a lot fun.

The only gotcha is that the FPGA onchip memory is OTP, so it should either be loaded by external CPU over SPI, or from external SPI Flash, in both cases the SPI pins are user defined IO after bootstrap. Or then fixed configuration is burned into OTP.

One idea is that if we want the module to have some FIXED function that has to be burned into OTP, we add some known tested good usable "personality" along our custom design. So after that the FPGA would check at boot up, if it switches to our code, or to the other personality. In such case the module would still be valuable and usable even if the code we burned into is not good, or not usable for us any more, we would just select the other personality, and could still have some use of hardware.

One example of the "know good personality" could be small soft-core that bootstrap its code from external i2c eeprom. Or then SPI slave peripheral for LED control.

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Patrick.pelgrims wrote 07/04/2015 at 15:14 point

Antti, can you tell more about the AVR port?

  Are you sure? yes | no

Antti Lukats wrote 07/04/2015 at 11:15 point

1280 LUT's is sufficient for small soft-processor, so you are not limited to pure hardware design, but can create customized soft-cores that use your own peripheral IP core, or the hard-ip block in the ice ultra. I have old code that was workin in ice65, optimized AVR core with simple fast GPIO, this all can be used or re-used.

If going back in history then this FPGA is 16 times large than the first Xilinx FPGA's (XC2064), plus there are 14 small dual port RAM blocks, and two internal oscillators (10KHz and 48MHz).

This design is I/O limited and hard tailored for minimal size and max I/O at lowest possible self cost price, all components (except PCB) cost with digikey pricing below 1.50 USD. This is pretty amazing.

Caveat: if using DIPSY as "SPI peripheral" then as I/O we have 6 pins only. When using external SPI flash for booting, then we have max 8 I/O (2 are shared with spi miso-mosi). Only when the internal OTP configuration memory is blown we have all 10 I/O pins fully usable.

Still at this size and price, its not that bad.

On my personal project there is pic from the ice65 stamp that has FPGA of similar size, and does run Basic programs on the embedded soft AVR soft-processor core.

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Eric Hertz wrote 07/04/2015 at 14:13 point

So then, when implementing e.g. an AVR... would you use a portion of the RAM for program-memory? That, then, would be loaded from an external SPI flash?

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Luke Gary wrote 07/04/2015 at 15:25 point

If you have access to the avr core, why not modify it to pull instructions from an external spi flash? Im sure it wouldn't be terribly complex. you may even be able to support spm instructions. Just deal with the added instruction fetch time.

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Eric Hertz wrote 07/04/2015 at 15:46 point

Ahh, right... entirely doable, probably, in an FPGA. These things are an entirely new concept to me. Clever.

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