Germanium ECL

How fast can germanium transistors compute ? And how much current will that draw ?

Similar projects worth following
While discovering the amazing world of germanium transistors during the germanium clock project, I came across high-speed germanium transistors (AF138, AF200 then AF240). At the same time, I examined ECL gates and the two concepts collided in my brain.
Then, I found Dieter's experiments (
Given that a Cray-1 is mostly a steaming pile of (N)OR3 ECL gates (and 1024-bit latches), it became obvious that it is possible to design a rather fast computing unit (ALU ?) with germanium transistors.

Here, I'm scratching a "proto-computing" itch that is rooted in the 50s and 60s, as explained on Wikipedia:

Another version (with significantly different resistor values) found at

Here, silicon NPN transistors are used but ECL was invented around 1955, when silicon transistors were not really working (and PNP was the king). This means that there must have been ECL circuits with Germanium PNPs.

Back to 2016: my friends here play with discrete transistors, mostly with DTL circuits: #AYTABTU - Discrete Computer, #The T-1: A discrete 8-bit Stack Computer or #Germanium Calculus use pull-up resistors and reach a few MHz.

Now, I have come across a supply of PNP germanium transistors, mostly for analog and radio applications:

  • AF138 (25V hFE=60...100, 60mW 40MHz)
  • AF200 (25V 10mA 225mW hFE>30, PNP germanium mesa transistor intended as TV IF amplifier, 1963-1965, freq. varies depending on the sources: 35? 100? 200?)
  • AF240 (15V, 10mA, hFE=25, 60mW) reaches 500MHz (at unity gain)

I also have some AF178 (180MHz, PHILIPS) AF137 and G106T (β around 60, 35MHz) but not enough to make something significant. The AF138 will do the bulk of the processing with some help from the others.

With >35MHz transistors, it must be possible to create pretty fast gates, no ?

From :

The 7090 used germanium alloy-junction transistors and (faster) germanium diffused junction[5] drift transistors. More than 50,000 in all.[6]

The 7090 used the Standard Modular System (SMS) cards using current-mode logic[7] some using diffused junction drift transistors.[5]

so YES there was ECL with advanced Germanium ! "Drift" technology was one of the last before Silicon took over (and powered CDC's 400K-transistors behemoth)


  • I got a new oscilloscope (4×300MHz, the beloved 2465) and a 11302A (advertised as capable of 4×500MHz).
  • I found a DDS that can reach 200MHz (stable level up to 70MHz)
  • I also found more AF240S...
This means I won't be limited by the AF138's low speeds !

1. Inventory
2. Starting to "get" ECL
3. If in doubt, try to investigate how Seymour Cray would have solved the problem.
4. Inventory #2
5. Fastest Germanium ?
6. The "language" of ECL
7. Register set musings...
8. More ECL musings
9. Advice from a germanium specialist
10. Inside the mesa can...
11. Complementary ECL


Datasheet (includes AF240 and AF279, close to AF280)

octetstream - 48.26 kB - 11/08/2016 at 05:06

Preview Download

View file

  • Complementary ECL

    Yann Guidon / YGDES12/30/2016 at 08:06 0 comments

      One of the first things that caught my eye, when I did some preliminary research, is the beginning of the Wikipedia page about ECL's history:

      Yourke's current switch was a differential amplifier whose input logic levels were different from the output logic levels. "In current mode operation, however, the output signal consists of voltage levels which vary about a reference level different from the input reference level."[16] In Yourke's design, the two logic reference levels differed by 3 volts. Consequently, two complementary versions were used: an NPN version and a PNP version. The NPN output could drive PNP inputs, and vice versa. "The disadvantages are that more different power supply voltages are needed, and both pnp and npn transistors are required."[9]

      Can you hear my headgears spinning ?

      The provided schematic was actually very tempting:

      I'm still confused about the reference things but this got me thinking.

      Unfortunately, the link to the original paper is down and I can't get the PDF.

      E. J. Rymaszewski; et al. (1981). "Semiconductor Logic Technology in IBM" (PDF). IBM Journal of Research and Development. 25 (5): 607–608. doi:10.1147/rd.255.0603. ISSN 0018-8646. Retrieved August 27, 2007.

      But there is a very good reason to use this alternating method : save on the output/buffer/emitter follower transistor (when the fanout is 1 or 2).

      For the Germanium version, I only have PNP types. NPN are too rare and out of price for this idea so I'll stick to the classic version.

      But I'm planning a Silicon version and guess what ? PNP and NPN are about the same price !

      The complementary ECL idea is why I got a bunch of BC549C and BC559C : not as fast and shiny as the AF240 but dirt cheap and flexible. Rated at 250MHz "only", they have a much better amplification that compensates and makes them more efficient as general-purpose switchers. They would probably consume less current (save power) and require less buffers.

      Now there is a little problem : for the alternance to work, there must be an even number of "stages" to pass through. Fortunately,

      1. the "buffer" can be used to skip an alternance
      2. there are circuits that naturally fit !

      One good example of 2) is the DFF gate as described at

      (thanks to @Ted Yapo for the link at )

      Do you see those red and blue lines ? Well they can be reorganised a bit but everything is here !

      The blue lines can come from NPN gates and the red lines from PNP gates. With one exception (the clock), all the gates go to a complementary gate (PNP to NPN and vice versa). The clock case can be solved by a differential clock signal.

      So a one-bit synchronous memory can be designed with 3 PNP gates and 3 NPN gates, each with 3 (or 4) transistors.

      I don't think it's a coincidence since I have vague memories about this circuit that I saw long ago and was coming from IBM. The same company that created ECL's ideas...

      I write all this here because I haven't yet created a project page for the silicon processor but that's something I'll definitely experiment with !

      If the prospect of a 250MHz "only" transistor is worrying, worry not : there are faster transistors (but they are more expensive) and the KSP10 is rated at 650MHz. This will be a welcome speedup for the critical datapath (the adder). And if it's still not enough, the BFR96 is rated at more than 3GHz. Damn, my DDS can only reach 200MHz, I guess I'll have to create oscillators with these very same UHF transistors...

      Still there is the old problem of feeding this speed demon with data and my fastest SRAM chips reach only 250MHz (the speed of the Cray-2).

  • Inside the mesa can...

    Yann Guidon / YGDES12/26/2016 at 21:02 4 comments

    The question of soldering the pins raises the issue of thermal damage, so I looked at the fabrication of the "mesa" type of transistor. I have found quite a lot of informations (thank you Google) but nothing beat "looking by oneself". So I opened on transistor and struggled to make a suitable picture, without dedicated tools...

    The wires are really thin ! And they meet at almost the same place, it's hard to distinguish even with optical help...

    There are 2 wires, connected to 2 pins. I believe that other than mechanical stress, it's fine during soldering. The wires are straight and can break but the heat might not travel enough through it.

    The other two pins are a different story. The "can" pin (who can tell me where to solder it ???) can take the heat but shoudn't get too hot, for many reasons.

    The fragile part is the collector (?) : it's the slice of germanium that is directly bound to a pin, and that might propagate the heat to the whole semiconductor. This is the pin to protect with a thermal clamp while soldering...

    I broke a few parts but this analysis should help me avoid damage during assembly.

    And i still don't know what should be connected to the "package" pin...

  • Advice from a germanium specialist

    Yann Guidon / YGDES12/21/2016 at 19:56 13 comments

    Is there anything to be careful about, when dealing with Ge transistors ?

    According to a retired engineer, soldering is tricky. I know Ge is very temperature-sensitive but he advised to not cut the leads. I'm still not sure about the exact meaning but Ge transistors can easily get destroyed during soldering. The soldering iron should be set to the lowest possible temperature, and I will find a way to cool the part down before and immediately after the joint is made...

    Who else can share their precious advices ?

    Now I get it why transistors were socketed back in the days...

    And this might be a solution. High frequency signals require short leads and the transistors should barely sit above the PCB plane to keep lengths and traces as short as possible. I'll have to find thousands of individual female sockets that I solder in the PCB holes. I have a "small" stock, maybe a thousand of them, but that is far from enough for a whole system...

    (picture found on eBay)

    I use these a lot to make prototypes, they are very handy. Unfortunately, all I can find (yet) is small sockets assembled in one (or two) row with 2.54mm spacing. Any hint for where to find individual pins ?

    Furthermore, I would cut the smaller end because the larger socket part would go through the PCB. That's a lot to cut...


    I have about 4K receptacles of this kind:

    First problem : I only have 4K. The AF240 has 4 pins so that's only enough for 1K transistors (barely enough for the register set alone). I got at least 8K AF240 (see below to see how it looks like) so I'd need a crazy 32K receptacles!

    Second problem : To get enough receptacles, I'd have to spend about $200 (that's chinese dollars, you know, you get what you pay for...)

    Third problem : Reliability. The transistor doesn't move much but... multiplied by 8K, it's a recipe for catastrophe ! I should rather make small modules with a dozen of transistors and test them well (eventually replace a failed part).

    Using receptacles, a vibration, a mishandling or any physical influence could perturbate the circuit, making it hard to use. I'd rather damage a few transistors before use, than spend all my time guessing with can got slightly upset...

    Concerning soldering : I did some research of the "mesa" technology and it does not seem to be particularly fragile (compared to others) so I'll make a bet by carefully soldering.

  • More ECL musings

    Yann Guidon / YGDES12/21/2016 at 18:53 0 comments

    I love logs !

    I write stuff I think, and when it's over, it makes me think more...

    The last log "Register set musings..." now looks somehow ridiculous to me. I blindly applied the approach I used for the relay version (#YGREC16 - YG's 16bits Relay Electric Computer) but the fanout tree becomes incredibly unsustainable. So I went back to the sketchpad and figured another latch topology.

    Still 6 transistors at the core, but organised differently, using a single-ended latch signal. This shrinks the driving logic significantly. Actually, the transistor count doesn't change, I have moved a "feature" closer to the latch cell, but I have also moved other things.

    I start to play with transistors in series to create AND functions and applied this idea to the output buffer as well : a double wired-OR now replaces the two MUX8 for the read ports. All I have to do now is create three DeMUX8 to drive the respective enabling transistors, and each output of the DeMUX8s have a fixed fanout (16 for 16 bits).

    Initially I had put the S (select) transistor at the low-side of the AND string but realised that the fanout would be always 2, since the base current would flow through both sides of the cell.

    With the high-side version, the current flows either through the left or the right side because D and /D are mutually exclusive.

    I am deliberately choosing asymmetric, non-ECL signals as a compromise between speed and parts count. I know I'll have a few issues with signal levels/swing because the bases will end up at different voltages, but I'm ready to increase the signal swing. I just want to keep the parts count as low as reasonably possible, without using xTL circuits...

    20161225: More thinking

    I now get "why" the "series" topology is often avoided, at least with bipolar transistors. The base current (the switching control signal) goes to the emitter, and with a hFE of 20, the margin is reduced. The bipolar version with higher gain will probably solve this, thanks to lower control current (better sensitivity) but I have yet to solve the current issues.

    For the input ports, D and /D will inject some current (base to emitter) and slightly increase the common floating node's voltage. But since D = / (/D), there is always current (of roughly the same value) going through one of the branches. There shouldn't be much problems (except maybe during state changes) and the common node voltage should remain the same (more or less).

    Things get ugly at the output. Base currents everywhere and necessary level shifting... Unless I shift the Vo node down to 0V ?

  • Register set musings...

    Yann Guidon / YGDES12/12/2016 at 01:38 0 comments

    The critical part of the "bitslice" architecture defined by #AMBAP: A Modest Bitslice Architecture Proposal is the register set. It uses quite a lot of parts ! An 8-registers implementation with 16 bits each requires 128 bits of storage ! So that's a critical part to optimise, for all kinds of good reasons: parts count, power draw, cost, space and of course : speed...

    So what's the smallest bit-storage element ? The R/S flip-flop requires 2 storage elements and 2 "upset" or "override" transistors. A 128-bits set requires 512 transistors... yet it could be worse. And I don't even count the "interface"/buffer transistors (that's 640 now).

    That's only 5 transistors instead of the more complex structures (such as the flip-flop implemented by Dieter)

    But I can't really afford 9×128=1152 transistors. Well, I could but if I could avoid it...

    Because the latch is only one element : we have the write select and the two read select circuits !

    The write select needs one transistor to drive the set line and another to drive the reset line, that's 6 transistors (plus the output buffer). This is now somewhat equivalent to Dieter's circuit (with only one output buffer transistor).

    However Dieter's circuit is fully differential and requires two differential inputs, or 4 wires, which also increases the number of driving transistors. The differential LD signal might be the hardest part because the D input is a simple value that can be "faned out". The clock signal however must be steered to the appropriate register (let's say one of the 8 registers). For the simpler R/S flipflop, I think I have found a simpler method: it's unipolar and uses less transistors (again, buffer transistors are omitted):

    This is another conjunction between my relay musings and Dieter's experiments (who coined the relay/ECL equivalence for decoders)

    The D and /D inputs could be coming from a previous flip-flop, or even merged with the buffer outputs (I should check this and the voltage levels might be incompatible but hey... maybe complementary transistors could help here ?)

    The cool thing is the EN input : the A0-A1 inputs can take some time to settle (and ripple down the fanout amplifier circuits) and a single EN strobe will then propagate to only one output. The EN signal can come from the same signal that drives /LD of Dieter's latch.

    I'm OK to sacrifice a bit of speed in order to save transistors and I'm not sure this circuit runs as fast as a NOR3-only D-ECL circuit but I got fast transistors so what. Furthermore, this circuit seems to work as well for Silicon transistors :-) (it's only a matter of setting the correct bias currents and voltages)

    Parts count for the writer tree : 2 or 3 transistors per latch, depending on the necessity of a buffer. Maybe mixed PNP and NPN could be used to save more parts.

    The tree could be "cut" to reduce its height (in case it causes problems). Since 8×2=16 outputs are required, a 2-level system (with two 2->4 decoders) could be used... I'll see later.

    The read MUX tree reuses the same "unipolar" ideas, though NOR3s and NOR4s can also work nicely.

    Now, you can't deny that this circuit is pretty compact: it uses less transistors than NORx circuits and I'm ready to accept that it's not as fast as plain D-ECL.

    Cost for a tree: 3 transistors per latch. Total per bit : 3 for write, 5 for latch, 6 for read. That's 16 transistors per bit, or 2048 transistors (at least) for a 8×16 register set... and I didn't count the input/driver latch. This amounts to most of my stock of AF240...

  • The "language" of ECL

    Yann Guidon / YGDES11/13/2016 at 15:30 4 comments

    As I start to "get" ECL, I discover its topological language and various methods to do the same thing.

    For example a OR gate, without the common bias node of MECL10K, found in an old patent :

    So that's one thing to do : compare this topology with the common-zener one. As germanium is pretty sensitive, I wonder which circuit will work best.

    The latches are another concern, apparently there are a few ways to make them, and 6 transistors per latch seems to be the minimum (12 per DFF, similar to other technologies).

  • Fastest Germanium ?

    Yann Guidon / YGDES11/07/2016 at 21:08 0 comments

    How fast can germanium transistors compute ?

    This question might receive an answer soon.

    While visiting one of the few remaining electronics parts stores of Paris, I found that they have a little stock of Ge. And I got their last AF280. From the datasheets:

    This transistor is particularly intended for use in mixer and oscillator circuits up to 900 MHz in diode tuned tuners.

    So the intuition worked (higher number means better performance, right ?), this transistor is faster than the 500MHz AF240 (though only by 10% because its transition frequency is actually rated for 550MHz) and the datasheet claims a power gain of 16dB @800MHz (power gain of approx 40, or amplitudes 12 ?) to a 2K ohms load (compatible with an ECL gate impedance). Too bad my DDS can't go so fast, but I'll try to hack a picosecond pulse generator...

    I got 13 AF280 and if I don't make mistakes, I might be able to build two NOR2 or NOR3 gates. Enough to test some logic and/or a flilp-flop :-)

    It just appears now that the answer I might get is not of the kind I expected intially.

    With such fast transistors, my lab tools are already too slow. I consider building a picosecond pulse generator but that won't help much.

    Furthermore, if I build a globule that is clocked so fast, I have another problem : memories. Latency and bandwidth will be hard to match with the expected means and I'll have to resort to using fast silicon chips.

    20170106: I found a batch of AF439, roughly equivalent to the AF280/279, so I might be able to build more than a couple of gates :-)

    It's going to be fun, though, since the hFE is ">10" ( The frequency is rated at 400 and 800MHz depending on the sources, but this speed will be held back by poor amplification.

  • Inventory #2

    Yann Guidon / YGDES10/31/2016 at 15:18 0 comments

    (updated 20161230)
    (updated 20170106)

    So I got the 4-channels 200MHz DDS, the 4×300MHz scope, as well as a 2×200MHz DSO, and a new supply of AF240S.

    I can now choose between 3 classes of Ge transistors :
    • 1600 medium-gain but slow PNP G106T, AF137, AF138 (hFE >60, Ft < 50MHz)
    • 700 faster but lower gain PNP AF178, AF200 (hFE>20, Ft > 100MHz).
    • 10000 very fast, low voltage, low gain PNP AF240S

    The slow transistors can be used for I/O ports. For example keyboard input, LED drivers, GPIO, serial I/O... Probably using saturated logic as well, whereas the AF240 will use ECL.

    I wonder if I can make 25MHz synchronous counters. That would enable me to work with a VGA display, reusing some tricks implemented by @Ted Yapo for #PIC Graphics Demo.

    No idea about how to implement some memory, though. I don't want to suffer the magnetic/core memory hell... I will certainly cheat and use modern CMOS ASRAM :-)

  • If in doubt, try to investigate how Seymour Cray would have solved the problem.

    Yann Guidon / YGDES09/21/2016 at 23:20 0 comments

    @matseng just sent me this link:

    This is just awesome :-)

    25) Transistorised ECL/DECL logic is a nice playground
        for wasting time, money and components in a creative way.

    I feel vindicated !

  • Starting to "get" ECL

    Yann Guidon / YGDES09/20/2016 at 23:08 0 comments

    Having a Cray-1 type board and some documentation about it, it only came recently to my knowedge that it is mostly made of (N)OR3 ECL gates. What I didn't realise is that it's not comparable to, say, a 74F00.

    First, larger logic fanout : 3 inputs, instead of 2. It changes everything. Two dual NOR3 in ECL can do the same as 4 NAND2 in TTL, in the same package size. You can easily make a latch with bells and whistles, and less critical datapath than, say, what #NEDONAND homebrew computer can do...

    Second, you got complementary outputs. You can use the inverting or non-inverting output, or both. With NAND2 (74F00) you must waste another gate to invert it, and even risk adding jitter/glitches...

    This is another killer characteristic. OK ECL consumes more, and uses more transistors but it's not only faster, but uses less gates overall. So it now makes sense to me that Seymour Cray chose this, and trying to design a circuit with it shows that it's actually very sound.

    I have been wondering today how to design a 2^N multiplexer. This is simply a circuit that selects from one input out of 2^N. Nothing fancy but since there are alternate ways to design an ECL latch, I wondered if there was an ECL MUX2 topology. ECL does not allow a signal path to cross the gate directly so it must be "computed" by transistors. X = (A & S) | (B & /S)

    The transistor topology does not look good because the AND parts require two transistors in series. This is electrically more complex than the canonical NOR gate.

    Now what happens in NOR3 world ? A MUX4 would be originally written as

    X = (A & S1 & S2) | (B & /S1 & S2) | (C & S1 & /S2) | (D & /S1 & /S2)

    OK let's say that we have a (N)OR4 for the main output. The 4 inputs are fed by ANDs. But wait,

    X = A & B = /( /A | /B)

    So the ANDs can be transformed into ORs with more bubbles. And now comes the bubbles-pushing games !

    The ANDs will use the complementary output of the NOR3 gates, so this comes "for free". The AND's input bubble will come from the latch's complementary output. And S1 and S2 will use both complementary outputs. The MUX uses no inverter anywhere, and only 2 levels of logic gates !

    Close view of a Cray-1 IO board. Fairchild and Motorola ECL chips, the tiny black dots are 2-resistors divider networks for termination. CRI chips too...

    What's the pinout of the 16-pins small gates ? I can't make sense of it, 3 inputs + 2 outputs = 5 pins, add 2 for GND and Vcc. 2 NOR gates => 12 pins, 3 NOR gates => 17 pins. This does not match. Help.

    Drive strength is another convincing factor (for Seymour Cray at least). For long distance communication, just use the pair of complementary outputs and send them over a twisted pair. Add some termination at the receiving end and use the signal(s) you need.

    ECL gates are pretty sensitive and have low swing (the lower, the faster, and Germanium has a low threshold voltage). This helps with fanout, if the buffer transistor's gain is high enough. I wonder how many gates can be driven by my germanium transistors, the AF240 has a quite low hFE...

    Fanout is to be determined.

    Looking at Dieters's MT15, I think about @roelh's ALU with this picture:

    My brain did not "see" the propagate/generate units but the couple of MUX4 of the ALU. But I realise now that MUX4 trick might be the best idea so far, and it would save a XOR layer for one operand... And I've found that MUX4 totally ECL-friendly :-)
    The big problem now is to deal with all the fanout and control signals. Dieter had a LOT of troubles with that...

View all 11 project logs

Enjoy this project?



Bharbour wrote 12/21/2016 at 22:20 point

In the old days (50-60s) they used to specify using a pair of needle nose pliers or forceps clamped on the wire between the solder joint and the transistor to protect it from the heat. 

  Are you sure? yes | no

Yann Guidon / YGDES wrote 12/21/2016 at 22:23 point


I'll have to find something like that...

  Are you sure? yes | no

Similar Projects

Does this project spark your interest?

Become a member to follow this project and never miss any updates