The Rise and Fall of Pulses

A project in which I try to go faster and faster

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I have a few projects in mind that need either really short pulses, or pulses with really short rise and fall times, or both. There are a number of ways to create such pulses, from reed relays (!) to ECL logic and CML-output comparators to old-school unobtanium avalanche transistors and step-recovery diodes.

Generating fast pulses is one thing; measuring them is another. I think I'm going to have to boostrap some measurement equipment because I may have already exceeded the capabilities of a 1 GHz scope.

I'll see what I can do.

The details for this project are going to be in the build logs, each detailing one experiment on the way to ... well, to be honest, I'm not entirely sure yet.

Portable Network Graphics (PNG) - 88.77 kB - 06/01/2019 at 11:31


JPEG Image - 3.19 MB - 05/02/2019 at 17:53


  • Coincidence Detector I

    Ted Yapo03/21/2021 at 15:16 0 comments

    The last log was about a fixed-width short-pulse generator. I don't have the PCBs back to weigh in with the final results, but indications are that it will generate a brief, well-defined pulse width for each input edge. Using two of these, you can build a coincidence detector:

    There is one of the pulse generator circuits on each input. When an input transitions high, the corresponding pulse generator emits a short pulse. If the pulses overlap for long enough, the middle AND gate outputs a pulse, triggering the output pulse generator to create a pulse. This final stage could be replaced with something else, if you wanted.

    There is some dead-time, of course, but that just limits the repetition frequency.

    A larger problem may be metastability in the output stage. It's possible the input signals to be just inside the coincidence window, which could cause a short pulse out of the AND gate, leading to a metastable state in the output flop. I'm not sure how to deal with this.

    Ignoring the metastability problem for the moment, the idea simulates well:

    The bottom two traces are the inputs. The next two are the pulse generator outputs. Second from the top is the AND gate output, and the top trace is the output pulse.

    This is mildly interesting, but I would like to detect coincidence within a much smaller window.

  • CMOS Short Pulse Generator

    Ted Yapo03/16/2021 at 14:27 0 comments

    Someone asked me about making a short pulse generator -- a few ns width -- with CMOS levels. I had done some fooling around with this before, so I took the opportunity to play around a bit. Here's what I came up with:

    the idea is to use a 74LVC2G74 to trigger on an incoming rising edge. This sets the d-flop, since the D line is pulled high. An RC delay composed of R3/C6 delays the now low Q_bar output as it feeds back into the Reset_bar input of the flop. This will reset the flop after approximately 12 ns. Meanwhile, a second RC delay, R1/C3, delays the low-going edge of  Q_bar into the AND gate. For the brief period that the AND gate inputs are both high, the output of the AND is high, generating the output pulse. The pulse width is a function of R1, C3, and the input and output characteristics of the gates involved, so some tweaking is in order to get the exact pulse width you desire. It's also important to choose NP0 capacitors so that the delays will be stable with temperature.

    Here's an image of the prototype. I used a 74LVC1G00 NAND followed by a 74LVC1G04 inverter since I didn't have a 74LVC1G08 handy.

    and here's the output (bottom, red trace), input (top, blue trace), and flip-flop Q output (middle, yellow trace)

    The input pulse is from my siglent arbitrary waveform generator, and has slow 9 ns edges. The output pulse is 2.992 ns +/ 52.4 ps long -- the goal was 3 ns -- and it has a rise time less than 650 ps. Remember, this was with a 74LVC1G04 output, so with the 74LVC1G08, the rise times may be a little different, but it will be well under 1 ns.

    Note that the 453-ohm output resistor forms a 10x resistive probe when connected to a 50-ohm oscilloscope input.


    I designed a PCB to see what effect a proper layout has on the pulse shape. I also used a 74LVC1G00 followed by a pair of inverters from a 74LVC2G04 so that it can drive 50-ohm loads directly; a single 74LVC gate doesn't source/sink enough current.

    and here's the layout:

    in about a week, I'll be able to test it and see how it works.

    UPDATE 20210323

    The PCBs arrived today, but I had a difficult time with them. Once all the parts were soldered on, the board drew a lot of current, making me suspect a short. Some probing with a DMM showed one diode drop across Vdd/Vss, a sure sign of a backwards-connected IC. Sure enough, my footprint for the 74LVC1G00 was wrong, swapping Vdd and Vss. Oddly enough, I made this footprint a couple years ago for a project that never got off the ground, and it sat lurking in my library the whole time. Anyway, I reworked the PCB and got on with testing.

    How does it work? About the same as the prototype.

    The input edge from a Siglent DDS is shown in the top trace, and the output pulse is at the bottom. The pulse width, as measured by the scope, is 2.4 ns, a little shorter than the prototype. There's less ringing at the top of the pulse, and it's also a bit shorter than the original. You could increase the 10-ohm resistor to stretch it a bit.

    The repetition rate is limited by the reset pulse fed back to the flip-flop. Testing revealed that it can be driven at 59 MHz without issue:

    but at 60 MHz, every other edge gets dropped.

    Note that the amplitude is also higher at lower repetition rates. Could it be that current draw of the output drivers is causing the voltage to droop? The output drivers are pushing 5V into a 100-ohm load -- a 50-ohm series termination plus the 50-ohm term inside the scope -- so, that's 50 mA. The 74LVC1G04's on the output can do 32 mA each, so that's OK, but maybe getting the power to them is the issue.

    Also note that I'm driving the thing with a sine wave input here. My DDS only goes to 25 MHz for square waves.

    Is the PCB version better? The overshoot on the falling edge is only around 500 mV instead of 1 V, so that's better. Plus, the paralleled output drivers can handle 50-ohm loads.

  • OSH Park 4-Layer Coplanar Waveguide

    Ted Yapo09/10/2019 at 15:31 12 comments

    I've taken a few swipes at this, but think I finally have it nailed. Here's a tested recipe for 50-Ohm coplanar waveguide traces on OSH Park's 4-layer stackup.

    The ground plane for this line is on layer 2, i.e. 6.7 mils below the top layer.


    I set the gap to 6 mils somewhat arbitrarily. It's a little bigger than the minimum 5 mil gap in the OSH Park 4-layer design rules, but still small enough to matter for a coplanar waveguide.

    To get an estimate of the proper width, I first consulted a number of on-line or application-based calculators. I used an Er value of 3.66 for all calculations. Here is a summary of what they suggest for a 50-Ohm trace:

    • Chemandy Electronics: 13.6 mils
    • KiCAD PCB Calc: 12.55 mils
    • Saturn PCB Toolkit: 13.6 mils
    • AppCAD: 12.55 mils

    As you can see, there are a couple of different sets of equations floating around.

    Sonnet Lite Simulation

    I also ran a test in Sonnet Lite, and produced the following plot of trace impedance vs width. It suggests that 13.4 mils is the correct value.

    Test PCBs

    I had a batch of three boards made at OSH Park. These each had a 13, 13.5, and 14-mil trace to test. I ignored the 12.55-mil result from some of the calculators, assuming that the model they were using was inappropriate for this structure. I have read that some of the equations used in PCB calculators were originally derived in the context of integrated circuit design, and have difficulties with certain PCB structures, but who knows.

    There is no soldermask on the lines, so you have to be careful soldering around them. It is easy to bridge them with solder, and even blobbing some non-bridging solder on there will affect the impedance. I covered the traces with Kapton tape before soldering on the SMA connectors. I removed the tape before testing the impedance.


    I measured the traces with a Tektronix 11801 sampling scope and SD-24 20 GHz TDR head. You can see the raw 13.5-mil screenshots at the end of this post, but here's a graph summarizing all nine traces. I fit a line to the impedance vs trace width, and it intercepts 50-ohms at a width of 13.4-mils. This is, perhaps not coincidentally, the optimum width suggested by the Sonnet Lite parameter sweep.

    You can also get an idea of the deviation you might expect across a larger PCB, maybe on the order of a few tenths of an Ohm. I have no idea what the batch-to-batch variation will be like, and at $24 for a set of three PCBs, I'm not going to gather stats on it at the moment.

    What About Soldermask?

    So, this is a dilemma. The OSH Park 4-layer stackup uses FR408 substrate with well-defined properties to achieve repeatable high-performance. The dielectric has a known and predictable Er. The soldermask applied over the top does not have a known and predictable Er, and I suspect that the thickness is not terribly well-controlled, either. Soldermask in the gaps of coplanar waveguide will decrease the characteristic impedance of the trace. How large this decrease is depends on the CPWG structure and the nature of the soldermask. On 2-layer PCBS, I have seen the impedance decrease by a few Ohms when soldermask is applied. On the 4-layer version, since the gaps are wider compared to the dielectric thickness, soldermask should have less of an impact.

    Then, there's loss. I don't have any data on the loss tangent for soldermask, but I'm guessing it isn't great. But, there's not too much of it involved, I guess, so it may not  make a huge difference.

    So, the effect is probably "small" but a little unpredictable. On the other hand, without soldermask, the trace is subject to environmental contamination, which can also affect the trace impedance. It's a tough call.

    I guess I should make a test board to see what happens.


    Here are screenshots of the three 13.5-mil traces -- one on each board. You can see where I had to exercise a little judgement in placing the cursor to read off the impedance. I keep thinking I should write some code...

    Read more »

  • Air Line Coax from Brass/Copper Tubing

    Ted Yapo09/07/2019 at 23:10 0 comments

    You know you want to make some air-line coax for an impedance reference from brass hobby tubing. But, what sizes to use? I threw together a quick python script to find the characteristic impedance and cutoff frequencies for all the combinations.

    The script uses all the available sizes (metric and inch) of K&S brass tubing. Some sizes are also available in copper, and any of them could be silver plated, although this probably isn't necessary for short sections.

    I haven't built any coax this way yet, but now I know which sizes to select.


    The characteristic impedance of coax is given by:

    where D is the inner diameter of the outer conductor, and d is the outer diameter of the inner conductor. The diameter units cancel.

    Cutoff Frequency

    At lower frequencies, waves travel in coax in the so-called transverse electromagnetic mode (TEM), where the electric and magnetic fields are both perpendicular to the direction of travel (i.e. the coax). Above a certain frequency, called the cutoff, higher-order modes can also exist on the cable. These propagate at different speeds, and generally ruin your day.

    The cutoff frequency for coax is given by:

    with D and d in inches.

    In both cases, the code uses Er = 1.00058986, the value for air.


    The python code calculates the characteristic impedance and cutoff frequency for all the combinations of K&R tubing sizes:

    #!/usr/bin/env python3
    import numpy as np
    from fractions import Fraction
    # (name, OD, ID) inches
    US_idx = np.linspace(1, 21, 21)
    US_tubing = map(lambda x: (str(Fraction(int(x), 32))+'"',
                                  x/32, x/32 - 0.028), US_idx)
    mm_idx1 = [1, 1.5, 2, 3, 3.5, 4, 4.5, 5]
    mm_idx2 = [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13]
    mm_tubing1 = map(lambda x: (str(x) + '/0.225 mm', x/25.4, (x-2*0.225)/25.4), mm_idx1)
    mm_tubing2 = map(lambda x: (str(x) + '/0.45 mm', x/25.4, (x-2*0.45)/25.4), mm_idx2)
    tubing = list(US_tubing) + list( mm_tubing1) + list(mm_tubing2)
    Er = 1.00058986
    table = []
    print('       Inner        Outer   Cutoff     Z0')
    print('                             (GHz)   (Ohm)')
    for outer in tubing:
        for inner in tubing:
            if inner[1] >= outer[2]:
            Z0 = 138 * np.log10(outer[2]/inner[1])/np.sqrt(Er)
            fc = 7.51393 / ((inner[1] + outer[2])*np.sqrt(Er))
            table.append((inner[0], outer[0], fc, Z0))
    for i in sorted(table, key=lambda x: x[3]):
        print('{:>12s}  {:>12s}  {:5.1f}  {:6.2f}'.format(i[0], i[1], i[2], i[3]))


    Here are the results. For the really low-Z combinations, although the tubing would fit based on the nominal sizes, it would probably short out due to manufacturing tolerances.

           Inner        Outer   Cutoff     Z0
                                 (GHz)   (Ohm)
       8/0.45 mm        11/32"   11.9    0.15
            5/8"        21/32"    6.0    0.31
          19/32"          5/8"    6.3    0.33
           9/16"        19/32"    6.7    0.35
          17/32"         9/16"    7.0    0.37
            1/2"        17/32"    7.5    0.39
          15/32"          1/2"    8.0    0.41
           7/16"        15/32"    8.6    0.44
          13/32"         7/16"    9.2    0.48
      12/0.45 mm    13/0.45 mm    7.9    0.50
            3/8"        13/32"   10.0    0.52
      11/0.45 mm    12/0.45 mm    8.6    0.54
          11/32"          3/8"   10.9    0.56
      10/0.45 mm    11/0.45 mm    9.5    0.60
           5/16"        11/32"   12.0    0.62
    4.5/0.225 mm    5/0.225 mm   21.1    0.66
       9/0.45 mm    10/0.45 mm   10.5    0.66
           9/32"         5/16"   13.3    0.69
      4/0.225 mm  4.5/0.225 mm   23.7    0.74
       4/0.45 mm  4.5/0.225 mm   23.7    0.74
       8/0.45 mm     9/0.45 mm   11.9    0.74
      4/0.225 mm         3/16"   23.7    0.76
       4/0.45 mm         3/16"   23.7    0.76
            1/4"         9/32"   14.9    0.77
    3.5/0.225 mm    4/0.225 mm   27.1    0.85
       7/0.45 mm     8/0.45 mm   13.5    0.85
           7/32"          1/4"   17.0    0.88
          15/32"    13/0.45 mm    7.9    0.97
      3/0.225 mm  3.5/0.225 mm   31.5    0.99
       3/0.45 mm  3.5/0.225 mm   31.5    0.99
       6/0.45 mm     7/0.45 mm   15.8    0.99
           3/16"         7/32"   19.9    1.03
      11/0.45 mm        15/32"    8.6    1.05
      5/0.225 mm     6/0.45 mm   18.9    1.19
       5/0.45 mm     6/0.45 mm   18.9    1.19
           5/32"  4.5/0.225 mm   23.8    1.21
           5/16"     9/0.45 mm   11.9    1.21
           5/32"         3/16"   23.8    1.23
      4/0.225 mm     5/0.45 mm   23.6    1.48
       4/0.45 mm     5/0.45 mm   23.6    1.48
            1/8"         5/32"   29.7    1.54
       7/0.45 mm         5/16"   13.4    1.91
           5/32"     5/0.45 mm   23.6    1.95
    1.5/0.225 mm    2/0.225 mm   62.6    1.96
      3/0.225 mm     4/0.45 mm   31.3    1.96
     3/0.45 mm 4/0.45 mm 31.3 1.96
    Read more »

  • 2-Layer PCB Tests Revisited

    Ted Yapo06/18/2019 at 22:30 0 comments

    I send out another batch of 2-layer PCBs to test different coplanar waveguide geometries and SMA end-launch connector footprints. There are seven different CPWG widths and seven different footprints on the PCB. I populated one with $0.20 ebay SMA connectors for the first test. I'll compare with $2 name-brand connectors next, then maybe some good ones.

    It took two tries to make the boards this time because of sloppiness and an Eagle bug. When you copy a single via in Eagle, you get another one on the same net. When you copy more than one via at once, they all end up on another net, for instance GND1, GND2, etc, which aren't connected to anything. I quickly cut & pasted the stitching vias on either side of the CPWG traces, and didn't notice this before sending out the first batch of boards. This PCB was too simple to bother running DRC, which would have caught it right away :-(


    Here are the measurements, summed up in an animated GIF. This format really shows how the impedance changes with the trace parameters. In this case, I kept the CPWG gap fixed at 6 mil, and varied the trace width. A common geometry for 50-Ohm CPWG on 2-layer 62-mil PCBs is 32/6, a 32-mil wide trace with 6 mil gaps on either side. I found that when covered with soldermask, the characteristic impedance of such a trace is typically too low - a narrower trace is called for.

    The upper cursor is at 50.91 Ohms, and the lower at 49.3 Ohms. The long flat area is the CPWG trace, and you can see the impedance increase as the trace width is reduced. The best match to 50 Ohms is between 30 and 31 mils. 30.5 might be a good width to use. Of course, this is going to vary because of the somewhat random dielectric constant of FR-4, but at least it's a real data point.

    SMA Connector Footprint

    The other variable in this test is the shape of the SMA connector footprint. The footprint consists of a 40-mil wide pad to solder the SMA connector pin to, with gaps on either side. Because the pin and the connecting solder introduce capacitance to the structure, you have to widen the gaps to maintain 50-Ohms.  Here are two of the footprints, with 10-mil and 40-mil gaps. These views don't really show the vias stitching the ground planes on the top and bottom layers. The plane is solid on the bottom layer.

    In the animated GIF, you can see for the 40/10 footprint with 10-mil gaps, there's a very large capacitive (negative) dip at the footprint. As the gaps are increased, you eventually get an inductive (positive) bump.  In between, at around 40/20, you get a minimum bumpiness at the footprint. There's still some wiggling of a few Ohms, and a large inductive bump before the footprint (inside the connectors). These are $0.20 SMA connectors, after all, which I don't expect much from.

    Next Up

    I'm going to populate another PCB with $2 connectors and see what they look like.

  • 45 GHz SiGe:C ft Transistors: 75 ps Rise Time

    Ted Yapo06/17/2019 at 13:42 0 comments

    The 11 GHz transistors weren't cutting it, so I had to step up to some silicon-germanium-carbon transistors with a transition frequency of 45 GHz. Luckily, I'm currently experiencing 2019, and such things exist now. These PCB images all look the same, but here is the board:

    The circuit is very close to the previous one, except with a different footprint for the SOT-343 transistors and added sites for peaking inductors:

    The output transistors are a pair of BFP740ESD's, $0.54 each in single quantities. R1 and R2 are again 100 Ohms, setting the output impedance. R3 is 75 Ohms. They're driven in this case from and ADCMP607 CML-output comparator. The rising output edge from the transistors is under 75 ps, with the falling edge under 70 ps. 

    The transitions from the comparator are a relatively slow 120 ps or so (the datasheet says 160 typical), and this may be limiting the output transitions from the transistors. I'm going to spin a PCB for a ADCMP572 comparator with 35 ps transitions to see how much faster the transistors will go. Even as-is, this is fast enough to move forward with the design.

    The output impedance of the circuit is 100-Ohms, set by the collector resistors. When loaded by the 50-Ohm scope inputs, the outputs have a 1 V amplitude. This means they're 3V unloaded, which is exactly the design point: perfect.

    With the PCB layout, there is enough stray inductance that I just replaced the lumped inductors with 0-Ohm resistors; anything more caused undesirable ringing.

    The lousy look of the step is due to some reflections on the PCB. I rushed this one out, and made some layout mistakes. Maybe I'll take a little more time on the next one.

    The transistors have a maximum Vce of 4.2 V, set by internal ESD protection devices. I was able to run the output stage at a supply voltage of around 5 V, by which time it had achieved maximum amplitude. At around 5.5 V, the output started to tear:

    this example also had 6.8n peaking inductors on the board, which causes the overshoot and ringing. The interesting thing is the high-frequency noise, which could be avalanche breakdown of the ESD protection devices, high-frequency parasitic oscillations, or an artifact of the sampling oscilloscope interacting with the waveform. I think the lesson is to keep the supply voltage to 5 V or less, but this is enough to give the 3 V output swing.

    The bottom line is that this $1 pair of transistors do a better job than the $10 laser diode drivers I had been using. It's amazing to me that you can get these kind of speeds with discrete transistors, but you can.

  • SY88022AL Revisited: 40 ps edges this time, sometimes

    Ted Yapo06/05/2019 at 16:17 0 comments

    I finally got around to populating an updated version of the SY88022AL test board. The datasheet claims typical 25 ps (20-80%) edges driving 30 mA into a 25-Ohm load. I haven't seen that yet, but it's definitely closer than last time.

    In this updated version, I drove the part with a faster CML-output comparator. The ADCMP572 has typical 20-80% edges of 35 ps, according to the datasheet. Of course, the CML outputs don't drive enough current for my needs, otherwise I could just use the comparator as the driver. This is a SiGe part, so I was a little worried about over-cooking it with the skillet reflow process, but it seems to have survived, which is nice, because they're $20 each. I may end up moving them from board to board for different tests :-)


    Here's what the thing looks like -- simple, really. The comparator switches when the input crosses a threshold (set at 1V because the scope's clock output is 2V unloaded). For some reason when I made this board, I didn't use the internal 50-Ohm termination on the input pin. It doesn't seem to affect the operation since the clock output is properly back-terminated, but I'll use it next time, for sure. Then, I'll set the threshold at 500  mV. The CML outputs drive the input of the SY88022AL.

    I used a ADCMP607 comparator last time, with much slower transition times of 160 ps. I was ultimately not able to get the edges out of that board better than around 70 ps, although I may re-visit it at this point.


    Here's around the best output I could get from this version. The transition times are around 40 ps for 10-90%. Assuming a linear rise, this is roughly equivalent to 30 ps 20-80%. The datasheet claims 25 ps typical, and I could easily see losing a few ps in the cabling and connectors.

    What bothers me about the output, though, is that I can only get these edge speeds for what I would consider very low output levels. I changed the output driver current to see what effect this would have

    250 mV

    In this case, I adjusted the output current to yield a 250 mV output amplitude. The output is loaded with 74 Ohms (50 for the scope plus a 24-Ohm series resistor to match the 25-Ohm outputs to the 50-Ohm transmission lines), so this is only delivering 3.3 mA into the load.

    The datasheet numbers are specified at 30 mA, although they specify a 25-Ohm load, which equates to a 750 mV swing.

    In any case, with this output amplitude, the edge rate is 38 ps.

    500 mV

    Here, I turned the current up to yield 500 mV outputs. This is equivalent to 6.6 mA into the 75-Ohm load. The edg rates have dropped to 44 ps.

    750 mV

    At 750 mV output swing, equivalent to 9.9 mA into the load, the edge rates are now 51 ps.

    1000 mV

    Finally, at a 1 V output swing, the edge rate has increased to 68 ps. This is 13.2 mA into the load.

    At this level or higher, the output starts to take on a different character - you can see the second, slow, slope in the falling edge. This may be where the output drivers have hit their compliance-range limit, although that really shouldn't happen until around 2 V outputs, according to the datasheet. Below these levels, the relationship between the output levels and transition times seems roughly linear, implying a slew-rate limiting. You can see it in the following plot, where a line had been fit to the lower three levels, with the 1 V output clearly an outlier.

    This model implies there's some fixed lower limit for the transition times, and that the edges have a fixed slew rate. That slew rate is around 10 kV/us, which is staggeringly fast.

    There's still something funny going on here, but I'm not exactly sure what. Maybe I need to revisit the previous version having had this experience.

  • 11 GHz ft Transistors

    Ted Yapo05/29/2019 at 14:14 0 comments

    So, after the last test with some through-hole BJTs, I spun a quick PCB to test faster SMD transistors. I had some BFU550A's on hand, which boast an 11 GHz ft compared to the 900-2000 MHz range of the KSP5179's. The output connectors are on the bottom of the board.

    The test circuit uses an ADCMP607 CML-output comparator to generate the differential outputs to drive the pair. The unloaded CML outputs have a 800 mV swing and 50-Ohm impedance. I used 75 Ohms at R3, and 100 Ohms at R1 and R2, as I had before. The ADCMP607 has typical rise and fall times of 160 ps (10% - 90%) according to the datasheet. The output pair has their own supply, which I set to 7 V for the following tests, while the comparator runs on 3.3V.

    I replaced C3 and C4 in this schematic with 1k resistors to act as 21:1 Z0 probes. This reduces loading effects and also divides the output voltage so that it can be measured on the sampling scope, which has a +/- 2 V input range.

    Bench Tests

    I hooked both outputs to input channels of an SD-24 sampling head in the 11801B scope. The outputs don't look spectacular, but they are certainly faster than the earlier test. In this case, the measured rise time was around 565 ps.

    The fall time is around 100 ps shorter, coming in at around 466 ps.

    The edges have a definite RC look to them - they start off good, then kind of fall off at the end. There is also an annoying extra step out around 3 ns. This is a reflection caused by my cheap ebay cables - they're around 47 Ohms instead of 50, which results in this kind of nonsense. I was able to simulate this in LTspice, below.

    Inductive Peaking

    When I threw this quick board together, I forgot about inductive peaking. If the slow transitions are indeed a consequence of an RC structure, adding an inductor in-line with the collector resistors can reduce the rise/fall times. Very roughly, the inductor allows the capacitive component to charge before loading the output with the resistance.

    I put together a simulation in LTspice to experiment with inductor values for peaking the outputs. I also added the transmission lines on the PCB and to the scope to model the step effect seen on the bench. A SPICE macro model for the BFU550A is available, which includes the package parasitics, yielding a more accurate result. Unfortunately, the models aren't licensed for redistribution - if you want to use them, you'll have to download them yourself.

    I also wrote some code using the LTspice .MEASURE statement to calculate the rise/fall times and slew rate of the outputs.

    Based on some initial cut-and-try tests, I came up with 5.6 nH as a good value for the peaking inductor. Here you can see runs with no inductor (1 fH), 5.6 nH, and 8.2 nH.

    You can also see the later step caused by a simulated 47-Ohm output cable. Setting the impedance of this transmission line to 50-Ohms eliminates the step.

    Zoomed in, you can see that without an inductor, the rise definitely droops a bit, with the 5.6 nH, the output looks better, and by 8.2 nH, the output overshoots.

    The measured rise and fall times also show the effect. The initial rise time of 434 ps is reduced to just under 300 ps by the 5.6 nH, with only around 25 ps more improvement going to 8.2 nH at the cost of more overshoot. On the other hand, overshoot is not likely to be problem for strobe pulses intended for diode sampling bridges -- it might even prove beneficial.

    Measurement: trise
      step    t90r-t10r
         1    4.3427e-010
         2    2.99055e-010
         3    2.73687e-010

    These simulation doesn't exactly match the bench tests in the no-inductor case. While simulations show a 434 ps rise time, I measured 565 ps on the scope. I'd like to see these numbers closer, but with all the non-modeled parasitics on the PCB, I'm not going to worry about it too much at this point. It might be something to revisit later.


    T-coils could theoretically produce better results than a simple inductor, but their math is complicated, and they're not off-the-shelf components....

    Read more »

  • I have to be discrete about this

    Ted Yapo05/24/2019 at 01:31 0 comments

    So, after evaluating all the parts I could find with fast edges, I've come to the conclusion that none of them are suitable for generating the strobe pulse required for a high-speed diode sampling head. The available parts - logic, comparators, and laser diode drivers - all have output swings which are too small. Time to use discrete transistors. At GHz speeds. Ugh.

    I started with what I had on-hand: a pair of KSP5179 transistors. They're rated at a minimum transition frequency of 900 MHz, which is around three times as fast as your ordinary 2N3904. Still, they won't do for the real sampling head. I'm looking at some 12 GHz ones at the moment, with 45 GHz SiGe units as a backup in case 12 doesn't cut it. For now, though, these T0-92 dinosaurs will serve as a proof-of-concept.

    In the current plan, a discrete-transistor differential output stage will be driven by the output of a CML comparator.

    Faking CML

    The first thing to do is to simulate a CML output swing without having to use a real CML part for testing. They're all blazingly fast, which would be wasted on these modest output transistors, and they only come in SMT packages. Instead, I added some resistors to transform the 0/3.3V CMOS outputs of a 74AC74 flip-flop into the 2.5/3.3V outputs (800 mV swing) of an unloaded CML output. The correct choice of resistor also provides a 50-Ohm output impedance like real CML. Those 180-Ohm and 68-Ohm resistors do the trick.

    I calculated the resistor values based on an assumed 22-Ohm output impedance for the 74AC74. It's really lower than this, but close enough. Maxima made short work of the required algebra. This kind of thing used to mean a half-hour diversion, including re-doing the manual calculations to catch mistakes.

    Differential Output Pair

    The output circuit is very simple. The two transistors are arranged as a differential pair. The bases are driven by the CML levels. The 75-Ohm and 100-Ohm resistors set the output stage current and voltage swing. This is a textbook diff-pair and it just works. Parasitics are probably bad on this layout, but there's not too much that can be done with these big through-hole parts. The pair is powered by a higher voltage than the CML stage, so it can have a larger voltage swing. That's the key thing that couldn't be done even with open-collector laser diode drivers; there are always protection diodes in the way.


    Here's what the output looks like. The top two traces are the outputs from the collectors of the transistors in green and blue. The bottom trace (pink) is one of the CML outputs - it's probed with a normal 10x probe with a long ground lead, so it shows some waviness. The rise and fall times of the outputs are around 1.7 ns. A rough back of the envelope calculation says that 12 GHz transistors might bring this into the 130 ps range, assuming everything else coöperates.

    This test used a 7-volt supply at Vcc, and produces a single-ended swing of around 2.9 V (5.8 V differential). I figure I need around a 6 V differential swing to drive a diode sampling bridge, so this is very close. A little tweaking of the output stage resistors would do it.

    The output, like the input, rides on a high DC bias voltage. That's OK -- it will be AC-coupled to the diode bridge. It's also important to note that the transistors must be kept out of saturation, in other words, the base voltage must be less than the collector voltage. On the screen, the red trace must be below the other two. You can see that the output supply voltage could be reduced a bit here.

    The outputs have built-in 1k resistors to make 21x Z0- probes when combined with 50-Ohm scope inputs. Luckily, the scope allows you to enter any number for the probe multiplier that you like. Note the 1.05 V/division scaling :-)

    Zooming in, we can get a better look at the transitions. They're actually better than I would have expected - nice linear ramps.


    The KSP5179 datasheet has a SPICE model, so I simulated...

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  • Laser Driver Strobe Pulse Generator

    Ted Yapo05/09/2019 at 13:41 2 comments

    This time around, it's a differential strobe pulse generator designed around two laser diode driver ICs. The SY88932L is intended for driving fiber-optic lasers at up to 4.25 Gbps. The key thing I wanted to test with this board was creating short pulses with clip lines. Using this technique, I was able to generate strobe pulses of 172 ps width. That's narrow enough for a 2 GHz sampling head.

    The laser driver claims typical rise and fall times of 65 ps (20%-80%), and I've measured around 100 ps (10%-90%). I made a simpler breakout to test just the SY88932L, but due to a supply chain snafu, I ended up having to remove the part from that PCB to populate this one.


    I like this part because the logic is simple and the outputs are open-collectors. Some laser diode drivers are internally terminated with resistors, or worse, some kind of active bullshit which interferes with using them as general-purpose drivers. I don't know how far above Vcc you can push the outputs - the datasheet claims they can only go to Vcc, but I'm guessing you could probably go a few hundred mV above before any protection diodes kicked in. I'd really love if these were just raw open collectors, but I don't think so. At some point, I'm going to have to add some really fast external transistors to boost the output swing. But for these early tests, this part works OK.

    Strobe Generator Circuit

    Here's the 172 ps strobe generator. The input is converted by an ADCMP607 comparator. This part has a single-resistor-controlled hysteresis level and CML outputs which can drive the other ICs directly. I've chosen the input threshold to suit the clock output of the 11801 sampling scope for convenient triggering. There are two SY88932L's on the board: the first one generates short differential pulses using clip lines, and the second is used as an output driver. This really is just a prototype/breakout PCB. It sucks when you have to spin a 4-layer PCB just for one test, but this isn't the kind of stuff you can do on a solderless breadboard :-)  The clip lines are just marked in text annotations; to Eagle, they're just normal traces. More on the clip lines below.


    This is the PCB, with the clip lines annotated. There's an LTspice simulation further down the page that shows more about how this works, but in a nutshell, transmission lines with shorted ends are used to define the pulse width. A current pulse into the open end of the line can only exist for as long as the pulse takes to travel the length of the line, reflect off the end, and return to cancel the original pulse. Since the CML signals are differential, two identical lines are required. In this case, the lines are just made with coplanar waveguide traces on the top of the PCB. The advantage of this technique is that the timing is easily controlled and stable.

    Tektronix used this technique to control pulses generated by step recovery diodes in their 1960s-era oscilloscope sampling heads. I found one for $30 on ebay so I can do a teardown - schematics are available, but they don't tell the whole story *at all*.

    LTspice Simulation

    LTspice has a transmission line component that makes modeling the important part of this circuit easy. The transmission lines on the left are the clip lines, while those on the right are just the connecting traces between the two ICs. The open-collector outputs of the laser driver are modeled with current sources. There's an internal 50-ohm termination (right) inside the driver's inputs. The clip line is AC terminated at the resting-state voltage of each line by a 50-Ohm resistor and shunt capacitor. This causes an inverted reflection from the end of the line.

    The output of the simulation shows what's going on. One of the input current pulses is shown in the top (red trace). The leading edge of the pulse switches the output at first, but eventually, the reflection arrives to cancel it out. On the trailing edge of the input pulse,...

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wmjlovesyy wrote 08/14/2022 at 07:01 point

This device can be used with 260ps propagation delay and 220ps rising and falling edges!!!

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Oskar Bäckström wrote 03/25/2022 at 08:30 point

This is great! I feel a kindled spirit here for fast pulses, sampling heads, step recovery diodes and whatnot. Any progress in the project? I have just read through all of it and wanted more :)

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terry.ho.cq wrote 07/26/2019 at 10:48 point

interesting and nice work. Hope to see how fast will adcmp572+SiGe:C transistor do, will keep update log? Thanks!

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Ted Yapo wrote 07/26/2019 at 15:19 point

spoiler: I haven't had a chance to write it up yet, but it didn't go any faster, still stuck at 75 ps. I want to try a higher-ft transistor next, and also need to check the layout very thoroughly, and probably simulate it. I am beginning to suspect that little mismatches here and there are eating ps. In one TDT test, just sending a signal through 3" of microstrip and two SMA connectors took the rise time from 30 ps to 60 ps. I am realizing that at these speeds I have to pay attention to very small details.

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Damian wrote 02/10/2019 at 07:13 point

interesting stuff. this may make a great TDR to measure impedance mismatch in high speed data lines and connecters. The question is if you can crank it up until you get a <10mm resolution and you really got something. I tested a commercial gear claiming 3mm resolution last year and it was even possible to see a via set too close to a differential line!

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Ted Yapo wrote 02/10/2019 at 13:13 point

That's a great idea. I hadn't thought of doing TDR. There are two aspects that make it particularly interesting. First, you don't need a compensated analog delay line like you do for a scope - simple digital delays before the pulse generator will do. Also, the time scale is doubled by the round-trip path; PCB features at 10mm come back after a leisurely 130 ps or so :-)

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Damian wrote 02/10/2019 at 13:59 point

I must admit I did not read the whole write-up so I also do not fully understand all details on how your measurement works but for the TDR I mentioned you need a high time-resolution signal of the voltage. If the goal is just to measure the distance to the first impedance mismatch (or cable length) then you are right but by sending thousands or millions of pulses down a line and shifting the capture point ever so slightly on each pulse (which is close to what you are doing right?) you get a high time-resolution waveform of the source voltage signal which of course depends on the impedance of the transmission line (and the termination).

If the source impedance is known then the impedances down the line can be calculated from the voltage that is reflected back to the source. It is explained better in this document: (check fig. 9)

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Ted Yapo wrote 02/10/2019 at 15:04 point

@Damian Yep, I've done primitive TDR with a scope before. I just hadn't thought of it as a use for this stuff. It's all very much a work in progress, but yes, the heart of it is a voltage sampler with a very small aperture (soon to get smaller) plus a variable delay to sweep the acquisition point relative to some trigger event (internal or external). For the TDR problem, a lot of complexities go away relative to trying to build an oscilloscope because you're generating the waveforms you're measuring. This eliminates the triggering problem and some other thorny issues.

Maybe I'll make a bumpy transmission line and try to measure it. Like splicing a few sections of 50, 75, and 93-ohm coax together. Something easy :-)

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Yann Guidon / YGDES wrote 12/28/2018 at 07:21 point

Oh, I'm VERY interested :-D

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Ted Yapo wrote 12/28/2018 at 18:49 point

Didn't you buy a Tek mainframe that can accept those really high-speed sampling plugins?

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Yann Guidon / YGDES wrote 12/28/2018 at 21:00 point

are we really going that route ? :-P

I have no idea of the reference of a sampling module for the 11k series... and it would need a crazy sampling probe at an insane price :-/

I am currently trying to reach about 500MHz with new active probes that will arrive soon and this is already unchartered territory for me...

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Ted Yapo wrote 12/28/2018 at 21:28 point

I have just resigned myself to measure everything with a 50-ohm input (at least for the moment). If I'm really worried, I'll add a 953-ohm resistor on the end of a piece of coax to make a 20x probe with 1k impedance. Any circuit that can't deal with that is weak ;-)

The 11800-scopes can accept an SD-30 sampler that goes to 40 GHz. Not sure which 11k you have...

The interface specs for these sampling heads are documented, which kind of makes me want to hack them onto the front of a cheap Rigol just for kicks.

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Yann Guidon / YGDES wrote 12/29/2018 at 20:58 point

Go ahead, I'll keep watching
////Grabs popcorn

Oh BTW I have a 11302A, not sure if it accepts many things...

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Yann Guidon / YGDES wrote 12/29/2018 at 21:00 point

Yeah the connector at the back is clearly not compatible with my mainframe...

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