The details for this project are going to be in the build logs, each detailing one experiment on the way to ... well, to be honest, I'm not entirely sure yet.
A project in which I try to go faster and faster
The details for this project are going to be in the build logs, each detailing one experiment on the way to ... well, to be honest, I'm not entirely sure yet.
I made a big mess on the bench, and got some decent data using the toy sampling head and the delay generator. Despite the look of a terrible layout, it manages 100 GS/s (equivalent time) and 180 MHz front-end bandwidth.
I tested the bandwidth using one of the previous edge generators that manages a modest 666 ps rise time. The resulting measurement has an approximately 1.97 ns measured rise time, which corrected for the rise time of the pulse itself is probably closer to 1.86 ns, from which we can infer a bandwidth of around 188 MHz. I estimated the rise time by least-squares fitting the best Gaussian step to the data (orange line). It's not a bad fit, really. This is probably due to all the errors summing into an approximately Gaussian response. The Central Limit Theorem saves my ass again.
Next, I tried a sine wave. My DDS only goes up to 120 MHz, which looks a little big on this timescale, but still recognizable. The individual samples are around 10 ps apart, although I didn't calibrate the timebase. That's 100 GS/s. Not bad for less than $20 in parts (single quantities).
As a final test, I looked at the output of my DDS set to the fastest edge it can produce, spec'ed at 8.4 ns. To get this trace, I stitched together five separate captures of 10 ns each.
The DDS says the step has an 8.4 ns rise time, but I haven't verified this with a "real" scope. I'll do that next time I'm in the lab. The Gaussian fit works well again on this step, estimating a 8.59 ns rise time. I'll write up how to fit a Gaussian step and estimate rise time from it at some point in the near future.
You can see more noise in these samples, because I used a tighter sampling loop that doesn't let the storage capacitor settle as long. There's a log upcoming about the details.
I'm also not sure how to automatically extend the sweep time like in this example. So far, it's been some trickery involving the DDS, but I really need a general solution. I can cascade the SY89296U programmable delay to give increments of 10.24 ns, but at around $10 each, it would be an expensive way to reach microsecond-length sweeps.
More research is required. And large government grants.
Until now, I believed that such a gate was the stuff of myth, like rainbow-farting unicorns. Now that I've finally found the 74LVC2G157, I'm going to take a little closer look at every horse I see, just in case.
So, here's the deal: the Y and Ybar outputs of the 74LVC2G157 2:1 multiplexer are as close to a differential output as you can find. I had previously measured the Q and Qbar outputs of a 74AC74 flip-flop and found them to have pretty low skew, but the fact that it's a flip-flop makes it a little difficult to use as an output buffer. The 74LVC2G157 seems even better, plus being 74LVC logic, has rise and fall times around 500 ps or so.
I designed a lavish breakout PCB to test this part mostly because I didn't feel like soldering the tiny SSOP pins by hand. The board has solder bridge footprints to allow any of the inputs to be connect to ground, +V, or the input signal. It turns out I only needed to test one combination. The logic of the mux is straightforward: Abar/B selects one or the other input to be routed to the output, when the Gbar input is low. The output is provided as Y and Ybar, which can be abused as a differential pair for all sorts of nefarious purposes. This is my kind of part!
By tying the A input low and B input high, the output follows the Abar/B input, producing a differential-output buffer. The output looks really good on the scope: the outputs transition in around 500 ps, and cross at about 1/2 the supply voltage, indicating a relatively low skew. I didn't measure the skew between the outputs directly, but it looks small enough to be useful. I'm not sure where the ringing is coming from; the outputs are probed with 10:1 resistive Z0 probes which should be fine at these speeds. It may be cheap RG174 cables from ebay - I'll have to re-test with some decent RG316 ones I have around somewhere. At least the ringing is relatively symmetrical and balanced.
Zooming in a bit, we get a better look at the transitions:
The traces don't cross exactly at 1/2 the supply voltage, indicating some possible skew, but it's relatively small. This could also be due to some other factors: I didn't check the two oscilloscope channels for perfect alignment, for instance. In any case, this is good enough to do some further work with. It's certainly better than tuning a couple of XOR gates.
Just to put this into perspective, this part is generating a 10 V differential step in half a nanosecond (it could be pushed to 11 V and still be within the recommended range according to the datasheet). This is plenty good enough to create a sampling pulse for an sampling oscilloscope of several GHz, since the diodes will switch on a much shorter segment of the transition. There was an old design for a sampling scope in Electronic Design (nearly 20 years ago now!) that achieved 1 GHz bandwidth with 2.2 ns transitions from the output of a comparator. This transition is nearly 5x faster. That's pretty exciting.
I also have some breakout PCBs for laser diode drivers with 25 ps transitions being fabbed at the moment, but this CMOS multiplexer might enable some incredibly-dirt cheap applications, like maybe a standalone (no oscilloscope required) TDR with spatial resolution in the cm range.
You know, in the rush I designed this PCB, I didn't check that the traces on the PCB are exactly the same length. There probably isn't much difference, but it could be a contributing factor.
I found some actual step-recovery diodes at Mouser. They're not the fastest ones available, with only a 150 ps maximum transition time, but that's still pretty good. They're available in SOT-23 and SC-79 packages, so I bought a few in each. I was able to test one today with the same setup I had used to test a 1N914 earlier.
Here's the input pulse (blue) vs the output (green). The diode has sharpened the fall time considerably, from 7.8 ns to 362 ps according to the scope auto-measurements at this time-scale. It's actually much faster than that.
The circuit to test this diode is the same one I used before:
In this case, the diode was in a SOT-23 package, so I used a little adapter PCB to mount it to two BNC connectors.
Here's the falling edge of that pulse again, at 200 ps/div. The scope now says it has a 278 ps fall time, but guess what? That's the fall-time of the scope itself! The diode probably has a fall time under the 150 ps maximum spec on the datasheet. I'll just have to find some clever way to verify it.
This seems promising. These diodes are only around $2 each, and are easily fast enough to generate strobe pulses for a 1 GHz sampling head.
I'm thinking I can drive one of these SRDs with a commercial MOSFET driver IC. The driver doesn't need to be particularly fast (a few ns transitions are fine), but needs to handle some hefty currents and have low jitter.
I got the delay line working tonight. It took a a little re-work on the PCB because I didn't understand the SY89296 datasheet. Luckily it was just one of the control lines and not the data, which is high-speed and impedance controlled and doesn't like to travel in blue wires very much.
I learned two important things. First, PECL is crazy power-hungry. I "debugged" the board for an hour looking for shorts or reversed components after noticing it drew 300 mA when I first applied power. I come from CMOS land, and expected an order of magnitude less current. Of course, once I dug through all the datasheets, I realized this was normal. The PCB is nice and toasty.
Second important thing: you have to use a *light* touch cutting traces on 4-layer PCBs. That second layer (in this case a ground plane) is only 6.7 mils under the top layer. It's very easy to cut down into the next layer and possibly short stuff. I'm used to hacking away willy-nilly with a knife, and that just doesn't cut it in this case (pun intended).
Anyway, I got the thing working. There's a 10-bit digital control and a 12-bit analog fine tuning of the delay. I measured approximately 9.54 ps per digital step, and around 28 fs per analog step, although individual steps of both both were lost in the jitter noise of the delay and the measurement on the scope I was using. Individual steps of the analog tuning will never be of much use - the intention is to simply use the analog tuning voltage to get the digital steps in nice 10 ps increments, although I'll certainly see how far I can push things.
The next step is to build a feedback oscillator with this delay line, and measure the oscillation frequency accurately to calibrate the delay.
Maybe I'll make a quick oscilloscope with it first just to see it work.
The sampling strobe generation work is taking some strange twists (details to come), but one branch I'm exploring is solidly traditional: step recovery diodes (SRDs). I have some real ones on order (not quite as unobtainium as I thought), but in the mean time, it turns out that the bog-standard 1N914/1N4148 type diodes can function as decent, if slow, SRDs.
In case you're wondering, those long leads are there for a reason (see below). There's not much to the test circuit - the diode is just shunted across the output of a pulse generator and measured with an oscilloscope.
Here's the measured output from the diode. Channel 2 (blue) is a copy of the output of the pulse generator (from another output channel) for reference. During the positive swing of the pulse, current flows through the diode. When the input polarity is reversed, the diode continues to conduct for a brief time, then suddenly "snaps off." You can clearly see the rapid drop in conduction, with the waveform becoming almost vertical at this scale.
Zooming in, we see that the rapid drop has a fall time of around 800 ps (ignore the automated measurement, it's looking at the overall drop from the top of the pulse). The pulse generator has a fall time of around 8.5 ns (compare the blue trace), so the diode has sharpened the fall time considerably.
This diode is very slow compared to diodes designed as SRDs, but it illustrates the concept.
Those long leads? They add some inductance which peaks the pulse a little. Here's the same diode with short leads. Note how the bottom edge of the pulse droops a little. In this regime, the inductance of a few cm of wire matters, and sometimes can be used to advantage. Of course, I found this by accident :-)
There is a paper out there on the internet somewhere that used a 1N4148 diode like this to produce a strobe for a moderate-speed sampling gate. Now I can't find it again, and it doesn't appear to be in my collection of papers. When it turns up again, I'll post the link here.
This is what I've been using so far, and will be until the new PCBs come back. It's a little primitive, and not entirely stable, but it allows adjustable delays with a resolution of tens of picoseconds. It's also really interesting to see how ground bounce and supply sag influence the high and low voltages of the "other" channel with these two output drivers in the same package.
The circuit has a pulse input and two outputs. You can tune the timing of one output relative to the other with a control voltage. The whole thing is breadboarded ugly/dead bug style on some copper clad. There's plenty of room for other stuff :-)
The circuit isn't very complicated. An NTE-618 varactor diode is used in an RC delay circuit to move the edge of one output relative to the other. The stationary edge uses a similar RC circuit with a fixed capacitor to place it approximately in the middle of the range of the variable output. You can tune the output over about 10 ns, and a 20-turn potentiometer allows setting the delay with a resolution below 50 ps.
The control voltage is non-linear and uncalibrated, so I tapped the outputs and monitor them on a 300 MHz scope to determine the relative time between the edges. The modern Rigol scope has better statistics on this kind of measurement than my ancient 1 GHz Tektronix, so I used it. Due to the large levels of jitter in the system, you have to average 20-50 measurements to get a stable result. This isn't as limiting as you might think, since you can use MHz repetition rates.
I had intended to retire this circuit and wait for the fancy new PCB to arrive, but after a brilliant observation by @salec on the last log, I think I'll do a few more experiments with it. The awesome idea was to calibrate delay generators by connecting them as feedback oscillators and measuring the resulting frequency. This frequency is related to the inverse of the delay time and frequencies are easily measured to parts-per-million accuracy.
I think I'll wire up a 12-bit DAC and op amp on the PCB to allow driving the varactor with 0-12V, hook up some kind of oscillator circuit, then try to calibrate the delay vs voltage. It's too bad my bench frequency counter doesn't have a PC connection. I might be able to use the spectrum analyzer, although it would take a bit of coding. Actually, it might be easiest just to find one of the OCXOs, TCXOs, or rubidium oscillators I have tucked away and throw together a quick frequency counter on an FPGA.
Of course, jitter will be around three orders of magnitude larger, but it remains to be seen what accuracy can be obtained by averaging many measurements. Wait, I'm getting ahead of myself. This PCB is a digitally-adjustable delay line built around an SY89296U programmable delay IC. This part, designed for adjusting clock edge timing, has a 1024-step digital delay control with 10 ps resolution, plus a 40 ps analog trim voltage input. I drive the trim voltage with a 12-bit DAC, allowing a theoretical delay step size of 20 fs. There will be non-linearities and jitter which limit the usable resolution to much greater step sizes.
The board has two 74HC595 shift registers to hold the 10-bit delay control word, plus a MCP4821 12-bit DAC for generating the fine-tuning voltage. Since the delay IC uses LVPECL signalling, LVCMOS translators are used on the input and output. This is really nothing more than a breakout for the SY89296U.
The SY89296U has 1024 nominal 10 ps digital delay steps, with less than 10 ps total jitter (2 ps cycle-to-cycle). It additionally has an analog fine-tuning voltage input with a resolution of 40 ps/V. I drive this input with a 12-bit converter with 0.5 mV step sizes, allowing for a minimum step size of 20 fs. This 20 fs number is somewhat meaningless, since it will be swamped by other issues.
The SY89296U has a maximum 10 ps total jitter. One of the translators has 5 ps, the other has 2 ps. I don't know about the 74LVC04 inverter at the end; I suspect it has around the same. I might be looking at 15-20 ps total jitter through the whole chain. That's not too bad, and the results can be improved by averaging over many measurements.
The accuracy of the generated delays depends not only on the resolution and jitter, but the calibration of the SY89296U. The actual delays generated can vary by about 20%, according the the datasheet. So, I need a way to calibrate the delays. So far, the best answer I have is another PCB I just sent out which has dual TDC7200 time-to-digital converters. This should be able to measure delays with 55 ps resolution and 35 ps standard deviation; it's possible I can achieve better results by averaging over many samples, but I'm not sure how far I can push it.
I'm also wondering about other ways to calibrate the delays. Any suggestions?
I think I need to dive into the literature at this point.
This was a new one for me. The LVPECL parts require special care and feeding, with their impedance-controlled and terminated differential traces and being referenced to Vcc instead of GND. I went with a 4-layer PCB, obviously. I don't mind paying extra for the 4-layer job at OSH park, I just wish there was a super-speedy option for this stackup.
Hey everyone, order more 4-layer PCBs, so they'll do one.
This PCB has been ordered as of 2019-02-09.
I don't think I've ever used the word femtosecond before. It's kinda fun.
This is the first in a few logs to document everything that went into getting the first sampling head to work. I needed a new edge generator with a build-in delay to line up the pulse edge with my sweep delay generator (details next log). I ended up making this with a 74AC14 and 74AC04.
The 74AC14 chain delays the input pulse, and you can select the polarity by choosing the output tap. One section of a 74AC04 is the output buffer/driver, and there's a resistive divider to provide a source-terminated 500 mV output into a 50-ohm load (100 mV unloaded). With the unused portions of the 74AC04 I made a "supply cleaner." This just connects unused *outputs* of the gates to Vcc and GND to essentially add more supply pins to the package. The MOSFETs in the output structures of those gates have a decently low impedance and hopefully help with the notorious supply problems of the 74AC family.
I measured the output of this new circuit with a few scopes, including the new sampling head.
(It's a modified TDS-754D, but don't tell anyone :-)
Here's the rising edge of the pulser on a 1 GHz scope. It looks pretty good except for a little bump about 1 ns after the edge. This isn't a reflection: there's not enough space anywhere to produce this timing. I think it's the 74AC04 itself. In any case, it's a feature on a short timescale that we can use to check other scopes. The rise time of the edge is 667 ps, not counting the contribution of the scope itself (it's likely under 600).
(It's a homebrew sampling head, tell anyone you like :-)
I painstakingly collected data for this edge using the same setup as before. It ended up being 97 points total, averaged over millions of input pulses. The calculated rise time for the sampling gate is 2.48 ns, for a bandwidth of 141 MHz. This is close to the 155 MHz I previously estimated with the fall time of a different pulse.
Interestingly, the little bump at the top of the pulse is just barely visible. I think this "scope" just doesn't have quite enough bandwidth to show the bump.
I'll come back to this image in a later log. There's a lot going on to capture this data.
(It's a modified DS2072A, but don't tell anyone :-)
This 300 MHz scope has just enough bandwidth to start to render the bump at the top of the pulse.
(It's a modified DS1054Z, but don't tell anyone :-)
On a 100 MHz scope, there's no bump on the pulse at all.
It certainly seems to behave like a 140 MHz scope - the captured waveform looks better than the 100 MHz commercial scope and worse than the 300 MHz model. So far, so good.
It was a long day in the lab, but I got it working. There are actually four oscilloscopes in this picture: three commercial ones, and one homebrew version on those copper clad boards. Right now, it has the most primitive interface you can imagine - you turn a 20-turn potentiometer to set the time at which you want to sample the input waveform, then read the voltage at that time off a voltmeter. But, even with this insanely stupid interface, it still has a higher bandwidth than the DS1054Z at the back of the table. I measured the bandwidth of the new sampling scope at 156 MHz. Not bad for a first "toy" version.
There are a lot of things to document, and it will take a little while to get it all down, but in a nutshell, I made an adjustable time delay for the x-axis that allows you to move the sample trigger pulse by about 10 ns, with resolution of maybe 30-40 ps (limited by jitter). Using this, I was able to capture a trace of the fall of a 844 ps pulse edge. The 90-10% fall time is 2.41 ns, but correcting for the fact that the input has a fall-time of 844 ps yields a 2.25 ns fall time for the sampler itself. Using the old 0.35/t rule, this front-end has a bandwidth of 156 MHz.
This plot was created from 79 data points taken by hand. For each one, the delay time was adjusted slightly with the potentiometer, then the voltage was read from a voltmeter. I wrote all the points down on paper. Because of the slow data collection, there's an insane amount of averaging going on. The pulse had a frequency of 1 MHz, and assuming it may have taken me 10-15 seconds to collect each point, there could be 10 million samples averaged to get this result. That's why you don't see any noise.
I think I'll have to automate this before the next test.
I have to document the variable delay and pulse generator used to capture this data. But right now I'm tired and am going to sleep.
One of the ways forward on this project is using diode sampling gates. Schottky diodes that can switch well into the tens of GHz are readily available, so it's just a matter of connecting them to the right stuff :-) I started out with a toy version - not that the 1N5711 diodes aren't capable, but the layout and pulse generator limit the circuit to lower frequencies.
The business end of the sampler uses six 1N5711 diodes: four in a bridge, and two to clamp the reverse voltage.
In the real thing, you'd use matched pairs (or quads) of diodes in SMT packages, but these work OK for breadboarding. I selected the six diodes from a lot of 50 by choosing ones that had about the same forward voltage. D1-D4 form a sampling bridge which is biased on during the brief sampling pulse. Between pulses, D5 and D6 clamp the voltage on the bridge to enhance isolation between the input and output. Ideally, these would be biased with split supplies, but for the initial tests, I left the bias supplies disconnected.
During the sample pulse, the 100 pF output capacitor sees the input voltage through the forward-biased diodes in the bridge and charges toward the voltage. The RC time constant of the circuit is based on the input impedance of 25 ohms (50 ohm source impedance in parallel with the termination) and maybe 10 ohms through the diodes. Combined with the 100 pF capacitor, this is around a 3.5 ns time constant. It doesn't matter that the capacitor doesn't charge fully during the strobe pulse, so this RC time constant doesn't set the front-end bandwidth. We can sample the waveform at the same point repeatedly until the capacitor settles to whatever resolution we need. This also does a lot of noise reduction by averaging.
I am also considering using a buffered version of the output voltage to boostrap the midpoint of D5/D6 instead of grounding it. You see this in some sample and hold architectures, but I'm not sure it's entirely needed yet.
The differential sampling pulse comes from a previous log, repeated here for convenience:
The rising edge of the input pulse creates a brief (approx. 2 ns) differential output pulse. A 2 ns sample pulse should create a sampler with around 200 MHz of bandwidth, although I haven't been able to test it that far yet.
I was able to test the sampler using two outputs from a DDS signal generator: one output is the signal to sample, while the second output generates the sample clock. Here's an example of how it works:
The yellow trace is the input waveform: a sine wave in this case. The magenta trace is the sample clock. At the rising edge of the sample clock, the input voltage is sampled and stored on the capacitor (cyan trace). You can see in the upper traces that the output is a "slowed-down" version of the input, since the sampling clock has been chosen to be slightly longer than 1/10 of the input period. In a real system, a trigger circuit and delay generator would create the sampling clock.
In the expanded traces (bottom), you can see how the output voltage changes in steps at each edge of the sample clock.
In this image, you can see the sampler "kick out," or perturbation of the input signal that happens during the sample pulse (lower yellow trace, directly under the trigger marker). This pulse feeds back into the measured system, which can be problematic. However, this kick-out can also be used to characterize the impulse response of the sampler. This may be useful later on.
From the above figures, it would be easy to mistake the sampling quantization with amplitude quantization and assume only coarse output steps can be created. This is not true; the examples above are simply to illustrate the behavior of the sampling gate. With a different sampling rate, a high-resolution version of the output emerges.
If you look carefully at the upper cyan traces in these images, you can see that two of them have a DC output offset. These...Read more »