The Rise and Fall of Pulses

A project in which I try to go faster and faster

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I have a few projects in mind that need either really short pulses, or pulses with really short rise and fall times, or both. There are a number of ways to create such pulses, from reed relays (!) to ECL logic and CML-output comparators to old-school unobtanium avalanche transistors and step-recovery diodes.

Generating fast pulses is one thing; measuring them is another. I think I'm going to have to boostrap some measurement equipment because I may have already exceeded the capabilities of a 1 GHz scope.

I'll see what I can do.

The details for this project are going to be in the build logs, each detailing one experiment on the way to ... well, to be honest, I'm not entirely sure yet.

  • Back to the beginning: ADCMP606 w/ 120 ps edges

    Ted Yapo2 days ago 5 comments

    I started this project with a pulse generator based on a ADCMP606 CML-output comparator. It was faster than my scope at the time, so all I could really say was that the rise-time was less than 350 ps or so. Last night, I found some quality time with the new scope, and measured the rise time of that circuit at less than 120 ps.

    At a longer timescale, the step looks pretty good, with minimal overshoot. It's a handsome pulse, attesting to the robustness of the comparator in the face of my inept board design :-) This comparator has a datasheet rise time of 160 ps, which implies typical Analog Devices understatement/over-performance.

    Overall, for a $6 (single-quantity) part, it's not bad at all. I think I'm going to make another revision of this board and release it. With a 120 ps rise-time, it's certainly good enough for testing oscilloscopes up to around 2 GHz.

  • Validating PCB Transmission Lines

    Ted Yapo6 days ago 24 comments

    So, I finally found some time to measure the impedance of a test PCB with the new TDR scope. I had made the PCB up a while a go to start validating the proper dimensions for controlled-impedance structures on the OSH Park board stackups, but didn't really have the equipment to measure it accurately until now.

    The TDR mode on the scope has direct readout in Ohms (vertical) and either time or length - if you know the velocity factor - on the horizontal. Of course, if you measure the time with the scope, and the physical length with a ruler, you can calculate the velocity factor - which will be my next step.

    The measurement results in 50.0 Ohms for the coax jumper, then 41.91 ohms for the PCB trace. It also shows that my PCB footprint for the SMA connector has a nasty reflection. I need to fix that.

    I used an on-line calculator to come up with the dimensions for this coplanar waveguide over ground plane. It  gave me a 14 mil trace width and 8 mil spacing for OSH Park's 2-layer stackup. I realize that this is just plain "random" FR4,  but I wanted to start with something inexpensive. I also realize that the dielectric will probably change from batch to batch, so I'm not going to chase this one too far. I'm much more interested in the 4-layer stackup on FR408 dielectric.

    The thing that bothers me, though, is that Saturn PCB toolkit, for example, says this line should have a 53.2 Ohm impedance.

    Calculators are stupid. I need to learn how to use a real electromagnetic simulation program.

    Maybe I was right?

    I did try to measure this with my own TDR before, but I didn't trust the results. I'll have to go back to my notes and see what I came up with before. I could have dismissed my results if I saw this large discrepancy before.

  • Good news and bad news

    Ted Yapo04/11/2019 at 01:00 0 comments

    The good news is that I can finally measure the fast and/or short pulses I've been working to make. The bad news is that they're not what they should be. The laser-driver pulse generator from a few logs ago measures out around 150 ps fall time. It should be much less than this - less than 40 ps, ideally. I haven't managed to measure the rise time yet.

    There could be any number of reasons for this, including my use of inexpensive - and physically large - passive components instead of high-frequency types. My PCB design probably doesn't help. There's a list of rise-times of various connectors and cables in the "black magic" book - I should add up the contributions from all the junk I have in the signal path, too.

    There is also a lot of jitter - I'm not actually sure I'm seeing the edge associated with the trigger here. If it were some later edge, that might explain much of the jitter.

    It's a little disappointing that the thing didn't "just work," but still exciting that I can see what's going on and iterate until it works.

    The machine behind the new measurements is this Tektronix 11801B with four SD-24 sampling heads. It arrived today from ebay, and I just finished a first test - all eight 20 GHz channels seem to work fine. The thing is a 60-pound monster, and I'm going to need to find something to put it on, because it takes up half my bench.

    I was in college around 1990 when this was new. It sold for around the same price as my entire education. We are so amazingly lucky to live in the time of ebay.

  • A diode bridge for sampling

    Ted Yapo04/04/2019 at 02:33 0 comments

    I found a very nice diode array which seems perfectly suited for a fast sampling oscilloscope front-end. The Skyworks SMS3923-081LF has four fast Schottky diodes in a dual series pair arrangement. It comes in a tiny 6-lead SC-88 case, and the datasheet has a model for the package parasitics as well as SPICE parameters. I made an LTspice component from it.

    At first I forgot to add the "p" to the CJO parameter, making it 0.9 Farads instead of pico-farads. This did not simulate well.

    The only thing I don't particularly like about these diodes is the diffusion transit time (TT SPICE parameter) of 80 ps. I wish it were smaller, but the truth is that I'm not going to get strobe pulses anywhere near that short, at least in the near future.

    Other than that, it looks like a winner.

    I'm still playing with some simulations of this part. I'll update the log with results soon.

  • Comparator Voltage Translator

    Ted Yapo04/01/2019 at 12:55 0 comments

    I'm documenting this here so next time I do it, I can just look this up. I needed a decently fast level translator from LVCMOS (3.3V supply) to CMOS logic run from a +/-2.5 V split supply. Running logic from a split supply is not something you see very often, so there aren't commercial translators which will do the job.

    I had a small bag of LT1016 comparators, so I decided to go with that. This comparator was very fast for its day, and it will do for now, although all these years later, there are certainly faster options available. In any case, proper layout is essential with fast comparators, and a healthy dose of positive feedback (hysteresis) keeps things stable.

    I didn't want to jam noise back into the input in this case, as you would usually do with a hysteresis arrangement from a non-inverting comparator output. Instead, since the comparator has true and inverted outputs, you can take feedback from the inverting output to the inverting input. This is positive feedback, and makes for some nice hysteresis, which also doesn't depend on the impedance of the input source. In any case, the circuit looks like this:

    I used wxMaxima to calculate the resistor values. First, the input divider, consisting of R1 and R2. I want this to terminate the input connector in 50 Ohms and also divide the incoming 3.3 V logic signal to a 1 V level. I chose 1 V because the common-mode range of the LT1016 only extends to around 1 V in this circuit (V+ - 1.5 V).

    Easy enough. 20 and 30 Ohms are standard 5% values, of which I have a lifetime's supply in 1/4 W through-hole.

    Hysteresis Calculations

    Solving for R3-R5, which determine the hysteresis, is a little more involved. I wanted the thresholds at 0.4 V and 0.6V, for 200 mV of hysteresis. I also wanted the impedance into the inverting input of the comparator to be relatively low, somewhat arbitrarily choosing 200 Ohms.

    The approach is to apply Kirchhoff's Current Law (KCL) to the feedback node and create an equation for each of the threshold states. An additional equation sets the impedance of the node to 200 Ohms.

    Simulation and Test

    Since the LT1016 is a Linear Technology device, it has a model in LTspice. Simulation revealed something I hadn't considered: the outputs are not rail-to-rail. I may have CMOS on the brain. Instead of providing 2.5 V when high, the outputs are closer to 1.2 V.

    The hysteresis levels in simulation are  420 mV and 558 mV. On the bench, the circuit worked fine with no problems observed. I don't have oscilloscope shots from the bench testing, but they were rather boring anyway.

    The circuit seemed to give nice, square outputs up to 20 MHz, then everything kind of started looking linear-ish. I've read that the gain drops of precipitously in these devices around this point, so it's not really surprising. When I get some more time, I'll go back and measure the performance up to 120 MHz or so, which is the limit of my current DDS generator.

    If I make this particular circuit again, I might use slightly different resistors to compensate for the lower output values. Using the LTspice simulations shows that the inverting output swings from -2.24 V to +1.22 V. Re-running the maxima calculations gives { R3 = 910, R4 = 270, R5 = 3600 }. Simulation with the new values shows thresholds of 418 mV and 606 mV. These aren't really that different from the ones I originally chose, so maybe it doesn't make much difference.

    In any case, I have a decent translator to connect things to logic driven from split supplies now. The output isn't fully rail-to-rail, but the +1.2 V high-level voltage is enough to meet the CMOS high-level input minimum of 1.0 V for the 74LVC gates I'll be driving with it. a more modern comparator might be even better.

  • Coiled Delay Line

    Ted Yapo03/31/2019 at 03:57 3 comments

    I was reading about coax delay lines today and was reminded about this kind of compact coiled delay line. It's essentially a coiled transmission line created by winding fine wire around a conductive tube. So, I made one - completely randomly - from stuff I had around just to see what it would do.

    To make the assembly, I soldered a length of 4.8 mm diameter brass tubing between the ground lugs of two BNC jacks, then wound a length of #36 wire on the tubing. I don't know the exact length of wire or number of turns, but the coil itself is 24 mm long. Some calculations show that this should be approximately 2.93 m of wire.

    The first test of the delay line was to hook it up to an oscilloscope to measure the delay and bandwidth. The delay line feeds channel 2, while a reference pulse, identical to that going into the delay line, is shown on channel 1.

    The delay on both the rising and felling edges is very close to 20 ns. This corresponds to a speed of 1.465 x 10^8 m/s, or 0.488 c in the wire. In the coiled structure, this is equal to 1.2 x 10^6 m/s or 0.004 c. That's pretty slow!

    This delay is equivalent to 4.03 m of typical coax with a velocity factor of 0.66.

    The bandwidth of the delay line can be estimated from the rise time of the pulses. Corrected for the rise time of the input pulse (9.25 ns), the output pulse has a rise time of 29.3 ns. This is equivalent to a 3 dB bandwidth of 11.9 MHz. Wow, that's not very good.

    I'm guessing that the bandwidth is degraded by capacitance between adjacent turns in the coil. Maybe it could be increased by adding a little space between them.

    When I get a chance, I'm going to measure the characteristic impedance of the line. Not quite sure the best way to do that yet. TDR or VNA?

    TDR Tests

    I fired up the #Tiny TDR this morning to test the characteristic impedance of the line. Here is a shot of the step from a 33 cm length of cable into the delay line. The Cyan trace (top) is the reference trace with just the cable connected to the TDR, and the green trace (bottom) is with the delay line connected. There is very little, if any, step at the boundary, indicating that the delay line has a characteristic impedance close to 50 Ohms.

    Here it is on a longer time-scale where you can see the end of the delay line. From a TDR perspective, the end looks like it's terminated with a capacitor, although this also mirrors the rise-time measurements taken with the scope. There's some deep connection here that's evading me at the moment. Again, the cyan reference trace is the output cable alone; the green is with the delay line attached. At this scale, you can see some slope to the trace before the end of the delay line.

    Finally, here it is without a 50-ohm terminator at the end of the delay line (cyan), and terminated (green). Again, it looks like little reflection from the terminator. You can still see some small rise and fall of the terminated trace, though. Maybe the impedance is a little higher than 50 ohms?

  • 74AC74 Differential Pulse Generator

    Ted Yapo03/30/2019 at 16:05 0 comments

    I had looked at the 74xx74 as a possible differential-output generator before, but the fact that it's a flip-flop complicates matters. I finally came up with a way to do it, though.  A fairly simple circuit using one flip flop creates short (3.2 ns) pulses from each input edge.

    The first flip-flop does all the work. The data line is tied high, so on the rising clock edge, the Q output goes high and Qbar goes low. Qbar is connected back to the CLRbar input, which resets the flip flop as soon as it has been set. The output from this flip flop is a differential pulse, but the Qbar output is slightly loaded. Because I had another flip-flop in the package, I added it as a kind of buffer on the outputs. The two outputs from the second flop should be more symmetrical.

    The outputs look OK for the kind of nonsense I'm trying here. One goes high and one goes low for around 3.2 ns.

    More interesting is the differential signal, estimated here by oscilloscope trace math.

    The differential pulse has an amplitude of  around 9.8 V (2x the 5 V supply), with a rise time of around 900 ps and a fall time around 550 ps. The width at the 50% threshold is 3.2 ns.

    The pulse width probably depends on voltage and temperature, and I'd expect a lot of part-to-part variation. But if you were driving a track-and-hold sampler where only the edges matter, then this should be fine.  It's not the ultimate in speed, at least with the 74AC version, but it would probably have faster edges if built with 74LVC parts. I'm going to have to try it now.

    The nice thing about this solution over the 74LVC2G157 I looked at before is that it takes care of creating a relatively short pulse for you. This could simplify things a bit - at least for some sampling topologies.

    If you were to use this to drive a diode sampling gate, you'd want to sample on the falling edge because it's almost twice as fast.

  • Maybe a 30 ps rise time - no way to tell (yet)

    Ted Yapo03/28/2019 at 15:06 0 comments

    I built a fast-edged buffer using a SY88022L laser-diode driver. The datasheet claims edge rates below 25 ps (20%-80%), which should be around 30 ps if measured 10%-90%. It seems to work OK, but the problem is that my best scope (so far) only has a rise time of around 300 ps, an order of magnitude too slow. This is a design I'll clean up and officially release once I'm sure it works - people might find it useful.

    The output driver has a differential CML input, so I used an ADCMP607 CML-output comparator as a buffer/translator from LVCMOS input signals. I'm not sure yet how much jitter this adds, but for just generating an edge without caring *exactly* when, it's fine so far. The ADCMP607 has built-in hysteresis you can adjust with a resistor. Looking at the image, I realize I populated that spot with a capacitor instead of a resistor. Oops. It may work even better with the parts in the right place :-)

    The thing runs on a 3.3V supply, and the input threshold is set at half the supply voltage. For a quick breakout-type test of the SY88022AL, it seems to work pretty well.

    There's sites on the PCB for a resistive pullup on the output to increase the voltage step, but I haven't tried doing this yet. The output has around a 1.3V amplitude into 50-ohms. Between the two differential outputs, this is a 2.6V swing. I need at least 3V to drive a diode sampling gate. I need to go back to my notes about this circuit and see if this is performing like I thought it would.

    The best measurement I can get of the output shows a 310 ps rise time. Of course, this is a 1 GHz scope, so this is really just a measurement of the scope itself, equating to a bandwidth of 1.13 GHz. I have every reason to believe the edge is significantly faster than this, although I have no way to prove it yet.

    This trace looks an awful lot like the following shot that was in the ebay listing where I bought the scope. This trace was taken with one of Leo Bodnar's pulsers which achieve 40ps outputs. Note the sloping before the edge and nearly identical ringing after. That must be the scope itself. This is a very good sign, indicating that I may have achieved a good short pulse. Depending on how I set the scaling, I can get the scope to read out measurements in the 280 ps range like in the photo.

    The scope's response makes everything at this scale "look" slow. Here it "looks" faster:

    I really need a faster scope in order to build a faster scope. I wonder what's on ebay today.

    EDIT: a friend with a 20 GHz scope has offered to measure this for me. Stay tuned.

  • Almost an oscilloscope

    Ted Yapo03/22/2019 at 17:53 0 comments

    I made a big mess on the bench, and got some decent data using the toy sampling head and the delay generator. Despite the look of a terrible layout, it manages 100 GS/s (equivalent time) and 180 MHz front-end bandwidth.

    I tested the bandwidth using one of the previous edge generators that manages a modest 666 ps rise time. The resulting measurement has an approximately 1.97 ns measured rise time, which corrected for the rise time of the pulse itself is probably closer to 1.86 ns, from which we can infer a bandwidth of around 188 MHz. I estimated the rise time by least-squares fitting the best Gaussian step to the data (orange line). It's not a bad fit, really. This is probably due to all the errors summing into an approximately Gaussian response. The Central Limit Theorem saves my ass again.

    Next, I tried a sine wave. My DDS only goes up to 120 MHz, which looks a little big on this timescale, but still recognizable. The individual samples are around 10 ps apart, although I didn't calibrate the timebase. That's 100 GS/s. Not bad for less than $20 in parts (single quantities).

    As a final test, I looked at the output of my DDS set to the fastest edge it can produce, spec'ed at 8.4 ns. To get this trace, I stitched together five separate captures of 10 ns each.

    The DDS says the step has an 8.4 ns rise time, but I haven't verified this with a "real" scope. I'll do that next time I'm in the lab. The Gaussian fit works well again on this step, estimating a 8.59 ns rise time. I'll write up how to fit a Gaussian step and estimate rise time from it at some point in the near future.

    You can see more noise in these samples, because I used a tighter sampling loop that doesn't let the storage capacitor settle as long. There's a log upcoming about the details.

    I'm also not sure how to automatically extend the sweep time like in this example. So far, it's been some trickery involving the DDS, but I really need a general solution. I can cascade the SY89296U programmable delay to give increments of 10.24 ns, but at around $10 each, it would be an expensive way to reach microsecond-length sweeps.

    More research is required. And large government grants.

  • There is a differential-output CMOS logic gate, after all

    Ted Yapo03/22/2019 at 15:39 1 comment

    Until now, I believed that such a gate was the stuff of myth, like rainbow-farting unicorns. Now that I've finally found the 74LVC2G157, I'm going to take a little closer look at every horse I see, just in case.

    So, here's the deal: the Y and Ybar outputs of the 74LVC2G157 2:1 multiplexer are as close to a differential output as you can find. I had previously measured the Q and Qbar outputs of a 74AC74 flip-flop and found them to have pretty low skew, but the fact that it's a flip-flop makes it a little difficult to use as an output buffer. The 74LVC2G157 seems even better, plus being 74LVC logic, has rise and fall times around 500 ps or so.

    I designed a lavish breakout PCB to test this part mostly because I didn't feel like soldering the tiny SSOP pins by hand. The board has solder bridge footprints to allow any of the inputs to be connect to ground, +V, or the input signal. It turns out I only needed to test one combination. The logic of the mux is straightforward: Abar/B selects one or the other input to be routed to the output, when the Gbar input is low. The output is provided as Y and Ybar, which can be abused as a differential pair for all sorts of nefarious purposes. This is my kind of part!

    By tying the A input low and B input high, the output follows the Abar/B input, producing a differential-output buffer. The output looks really good on the scope: the outputs transition in around 500 ps, and cross at about 1/2 the supply voltage, indicating a relatively low skew. I didn't measure the skew between the outputs directly, but it looks small enough to be useful. I'm not sure where the ringing is coming from; the outputs are probed with 10:1 resistive Z0 probes which should be fine at these speeds. It may be cheap RG174 cables from ebay - I'll have to re-test with some decent RG316 ones I have around somewhere. At least the ringing is relatively symmetrical and balanced.

    Zooming in a bit, we get a better look at the transitions:

    The traces don't cross exactly at 1/2 the supply voltage, indicating some possible skew, but it's relatively small. This could also be due to some other factors: I didn't check the two oscilloscope channels for perfect alignment, for instance. In any case, this is good enough to do some further work with. It's certainly better than tuning a couple of XOR gates.

    Just to put this into perspective, this part is generating a 10 V differential step in half a nanosecond (it could be pushed to 11 V and still be within the recommended range according to the datasheet). This is plenty good enough to create a sampling pulse for an sampling oscilloscope of several GHz, since the diodes will switch on a much shorter segment of the transition. There was an old design for a sampling scope in Electronic Design (nearly 20 years ago now!) that achieved 1 GHz bandwidth with 2.2 ns transitions from the output of a comparator. This transition is nearly 5x faster. That's pretty exciting.

    I also have some breakout PCBs for laser diode drivers with 25 ps transitions being fabbed at the moment, but this CMOS multiplexer might enable some incredibly-dirt cheap applications, like maybe a standalone (no oscilloscope required) TDR with spatial resolution in the cm range.


    You know, in the rush I designed this PCB, I didn't check that the traces on the PCB are exactly the same length. There probably isn't much difference, but it could be a contributing factor.

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Damian wrote 02/10/2019 at 07:13 point

interesting stuff. this may make a great TDR to measure impedance mismatch in high speed data lines and connecters. The question is if you can crank it up until you get a <10mm resolution and you really got something. I tested a commercial gear claiming 3mm resolution last year and it was even possible to see a via set too close to a differential line!

  Are you sure? yes | no

Ted Yapo wrote 02/10/2019 at 13:13 point

That's a great idea. I hadn't thought of doing TDR. There are two aspects that make it particularly interesting. First, you don't need a compensated analog delay line like you do for a scope - simple digital delays before the pulse generator will do. Also, the time scale is doubled by the round-trip path; PCB features at 10mm come back after a leisurely 130 ps or so :-)

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Damian wrote 02/10/2019 at 13:59 point

I must admit I did not read the whole write-up so I also do not fully understand all details on how your measurement works but for the TDR I mentioned you need a high time-resolution signal of the voltage. If the goal is just to measure the distance to the first impedance mismatch (or cable length) then you are right but by sending thousands or millions of pulses down a line and shifting the capture point ever so slightly on each pulse (which is close to what you are doing right?) you get a high time-resolution waveform of the source voltage signal which of course depends on the impedance of the transmission line (and the termination).

If the source impedance is known then the impedances down the line can be calculated from the voltage that is reflected back to the source. It is explained better in this document: (check fig. 9)

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Ted Yapo wrote 02/10/2019 at 15:04 point

@Damian Yep, I've done primitive TDR with a scope before. I just hadn't thought of it as a use for this stuff. It's all very much a work in progress, but yes, the heart of it is a voltage sampler with a very small aperture (soon to get smaller) plus a variable delay to sweep the acquisition point relative to some trigger event (internal or external). For the TDR problem, a lot of complexities go away relative to trying to build an oscilloscope because you're generating the waveforms you're measuring. This eliminates the triggering problem and some other thorny issues.

Maybe I'll make a bumpy transmission line and try to measure it. Like splicing a few sections of 50, 75, and 93-ohm coax together. Something easy :-)

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Yann Guidon / YGDES wrote 12/28/2018 at 07:21 point

Oh, I'm VERY interested :-D

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Ted Yapo wrote 12/28/2018 at 18:49 point

Didn't you buy a Tek mainframe that can accept those really high-speed sampling plugins?

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Yann Guidon / YGDES wrote 12/28/2018 at 21:00 point

are we really going that route ? :-P

I have no idea of the reference of a sampling module for the 11k series... and it would need a crazy sampling probe at an insane price :-/

I am currently trying to reach about 500MHz with new active probes that will arrive soon and this is already unchartered territory for me...

  Are you sure? yes | no

Ted Yapo wrote 12/28/2018 at 21:28 point

I have just resigned myself to measure everything with a 50-ohm input (at least for the moment). If I'm really worried, I'll add a 953-ohm resistor on the end of a piece of coax to make a 20x probe with 1k impedance. Any circuit that can't deal with that is weak ;-)

The 11800-scopes can accept an SD-30 sampler that goes to 40 GHz. Not sure which 11k you have...

The interface specs for these sampling heads are documented, which kind of makes me want to hack them onto the front of a cheap Rigol just for kicks.

  Are you sure? yes | no

Yann Guidon / YGDES wrote 12/29/2018 at 20:58 point

Go ahead, I'll keep watching
////Grabs popcorn

Oh BTW I have a 11302A, not sure if it accepts many things...

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Yann Guidon / YGDES wrote 12/29/2018 at 21:00 point

Yeah the connector at the back is clearly not compatible with my mainframe...

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