These files let you process VHDL files mapped to FPGA/ASIC gates, to:
- Simulate the circuit
- Perform static analysis of the netlist
- Extract dynamic activity statistics
- Verify that any internal state can be reached
- Alter any boolean function, inject arbitrary errors and prove your BIST strategy
- Extract logic traversal depth, detect unexpected logic chains and estimate speed/latency
- Inspect logic cones
- Ensure that the circuit is correctly initialised with the minimal amount of /RESET signals
- Detect and break logic loops
Some day, it could be extended to
- Pipeline a netlist and choose the appropriate strategy (will require detailed timing information)
- Transcode/Transpile a netlist from one family/technology to another
- Import/export to EDIF or others ?
The project started as #VHDL library for gate-level verification but the scope keeps extending and greatly surpasses the ProASIC3 domain. I also study the addition of the minimalist OSU FreePDK45. More unrelated libraries should be added in the near future, depending on applications : Skywater PDK and Alliance could follow. Contact me if you need something !