BeagleLogic Standalone

BeagleLogic, now as a turnkey and standalone 16-channel Logic Analyzer

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Three years ago, the BeagleLogic project showed how to use a BeagleBone as a 100MSa/s, 14-channel logic analyzer.

BeagleLogic Standalone is the next step in the evolution of BeagleLogic from just an add-on to the BeagleBone to a standalone logic analyzer in itself. It is based on the OSD3358 System-In-Package (SiP) from Octavo Systems and increases the specifications to 16-channels @100MSa/s and adds Gigabit Ethernet vs. 100Mbps on the BeagleBone(s).

BeagleLogic is not just about the hardware but also covers the software that runs on the BeagleBone as well. It will feature a new web-based front end built in React (which I am actively learning).

As of today (24th July 2017), the schematics for the BeagleLogic standalone board is complete and can be found in the "Links" section below the project gallery. Board routing is expected to finish soon.

The challenge that this project addresses is to make connected instrumentation affordable (BeagleBone with the BeagleLogic cape is one of the cheapest yet feature-rich logic analyzer out there), enable remote debugging of hardware projects and provide an unconventional web-based user interface for the logic analyzer.

BeagleLogic is not just a Logic Analyzer but a full-featured Linux computer in the same package. BeagleLogic enables the user to not just capture logic data but also analyze them on the device itself as the powerful sigrok set of tools can run on top of the GNU/Linux OS running on the BeagleBoard hardware enabling in-situ protocol analysis, all on the BeagleLogic hardware itself.

BeagleLogic's web interface is the first of its kind ( as far as I am aware ) and will enable a much smoother out-of-the-box user experience than conventional logic analyzers. Today's browsers are very capable and with BeagleLogic I want to prove that a good web interface for a logic analyzer is both possible and achievable.


To implement the BeagleLogic Standalone hardware I will be using the Octavo Systems' OSD3358 SIP [BeagleBone on a chip], as it incorporates all the essential components including the SoC, power management and DDR RAM and allows me to focus on the features I want to add.

1. Features

-> 16 logic channels @100MSa/s (vs max possible 14 on the BeagleBone)

-> Gigabit Ethernet Connectivity (vs max 100Mbps on the BeagleBone Black) via a Micrel KSZ9031 Gigabit PHY connected to the OSD3358 SiP. This will enable real-time sampling at higher rates than currently possible

I want to stress here that the 100Mbps link (either through Ethernet or USB - which is a little lower than 100Mbps) is a major bottleneck in getting data out of the BeagleBone. BeagleLogic can easily generate in excess of 100MB of data per second (that's 800Mbps!), and an interface that can get data out at the speed of 1000Mbps is a major improvement and should make sampling of 8 channels @100MSa/s in real time feasible.

-> 24-pin Expansion connector providing SPI, I2C, UART, PWM and GPIO ports for signal injection into host circuit

-> One USB-A host port for connecting external storage

->  Software Compatibility with the BeagleBoard ecosystem This will ensure that software designed to work with the BeagleBoard should also work with BeagleLogic out-of-the-box. 

2. Licenses

The software is licensed in a mix of MIT and GNU GPL v2 Licenses (the kernel driver is under GPLv2, the web interface is MIT licensed). The hardware is released under the CERN Open Hardware License.

3. Documentation

Documentation for the project can be found at the project wiki but is being migrated over to Read the Docs, and eventually will be served over Read the Docs at

4. Business Plan (also attached as a pdf in the "Files" section)

USP: In-situ protocol analysis (through the sigrok suite of software), networking capabilities enabling remote debugging of hardware projects, and the web-based interface (first-of-its-kind for a logic analyzer) at a very attractive price point near to, or a little bit above $100.

Target Market:  Makers, single-board-computer users (including the BeagleBoard and the Raspberry Pi) and beginner-to-intermediate level engineers looking for a capable and expandable logic analyzer on a budget.

Competitive Advantage:  There are a few logic analyzers in the up-to $100 category, including the Dangerous Prototypes' OpenBench Logic Sniffer, and BeagleLogic shall offer the best price-feature tradeoff in this category ( with 100MSa/s, 16 channels, large sample depth, networking capability for remote debugging and in situ protocol analysis). 

Product(s) to be sold:  The primary product in the BeagleLogic family of devices will be the BeagleLogic Standalone which will be the major source of...

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BeagleLogic Business Plan.pdf

Business Plan as per the 2017 Hackaday Prize Best Product requirements.

Adobe Portable Document Format - 132.38 kB - 07/24/2017 at 06:45



Complete Bill of Materials in CSV format

Comma-Separated Values - 5.91 kB - 07/20/2017 at 07:52


  • 1 × OSD3358 System-In-Package containing the TI AM335x ARM SoC, DDR RAM and TPS65217 PMIC
  • 1 × KSZ9031RNX Interface and IO ICs / Ethernet, T1, E1
  • 1 × SDIN8E2-4G 4 GB eMMC
  • 1 × 74LVCH16T245 Logic ICs / Receivers, Transceivers
  • 1 × MCP79410 Clock and Timer ICs / Real-Time Clocks

View all 41 components

  • Release to Manfacturing

    Kumar, Abhishek09/13/2017 at 16:35 0 comments

    Excited to announce that I have released BeagleLogic boards to OSH Park for manufacturing, and also ordered parts for the initial prototypes of BeagleLogic.

    The shared project for BeagleLogic can be found here:

    Here's a screen render of the final board:

  • PCB Almost There

    Kumar, Abhishek09/09/2017 at 18:22 0 comments

    Here's how the board looks, courtesy KiCAD's 3D renderer:

    It measures 10cmx6cm in size. I was able to pack everything in 4 layers.

    The board goes out for fabrication on Monday.

  • It's coming up

    Kumar, Abhishek09/02/2017 at 17:24 0 comments

    Here a screenshot of the routing in progress:

    I might have to use 6 layers instead of the original 4 to fully fit everything. I expect the routing to be complete by this week-end after which I will release the design to manufacturing.

  • Making a TCP Server for BeagleLogic

    Kumar, Abhishek07/24/2017 at 07:53 0 comments

    One of the bottlenecks when using BeagleLogic in conjunction with a PC is that unless you are using the web interface, the logic capture needs to happen on the BeagleBone (in an SSH shell) and then the captured file needs to be copied to the PC in order to view the capture using the PulseView software in the sigrok suite and do further post-processing.

    To merge these two steps into one, I am building a TCP server for BeagleLogic that will run on port 5555 of the BeagleLogic standalone. PulseView supports connecting to Logic Analyzers over the TCP/IP protocol, and hence I am building support for the BeagleLogic TCP protocol into libsigrok so that it can natively interact with BeagleLogic standalone, and support capturing logic data directly from the PC, skipping the intermediate step of copying the files from the BeagleLogic standalone onto the PC.

    The TCP server is built using NodeJS and is currently checked into the BeagleLogic repository. It can be found at -

    Now to make the TCP server work with PulseView and retrieve captures directly into it.

  • New Version of Documentation now online!

    Kumar, Abhishek07/21/2017 at 14:37 0 comments

    I am migrating the original content hosted at the BeagleLogic wiki over to a new hosted documentation at Please check it out at:

    Suggestions and Feedback welcome.

  • BeagleLogic Standalone featured on Hackaday

    Kumar, Abhishek07/21/2017 at 07:40 0 comments

    View the article here:

    Thanks to @Brian Benchoff for the Hackaday Prize entry feature blog article.

  • New Release of the BeagleLogic System Image

    Kumar, Abhishek07/19/2017 at 16:49 0 comments

    Announcing the release of a new System Image for BeagleLogic, which is now available here

    This release is based on Debian 9 (Stretch), which is the newest stable version of Debian GNU/Linux available.

    NodeJS in this system image is upgraded to the latest available v6.11 LTS release (it is used by the web interface)

    Also the sigrok components bundled in this image have been upgraded to the libsigrok 0.5.0 release which happened in June 2017. They incorporate new features and protocol decoding is expected to be faster as a result of the new protocol decoder API.

    The device tree overlay in BeagleLogic is now loaded using uboot cape overlay support which requires that one hold down the switch to boot from SD card by default. Alternatively one can also update the bootloader on the eMMC so that it can support uboot overlays.

    Login as root is by default disabled in the new system images for better security. Therefore the BeagleLogic image now allows attributes (samplerate, sample unit, ...) to be set through the default user without requiring root permissions. This also improves the quality of experience.

    It is highly recommended that users update to the new system image.

  • Schematic Completed

    Kumar, Abhishek07/14/2017 at 18:22 0 comments

    Today I completed the schematic.

    The completed schematic and design is online at

    Apart from 16 logic inputs, BeagleLogic standalone shall also incorporate a 24-pin expansion header that breaks out:

    • 1 UART
    • 1 I2C
    • 1 SPI
    • 1 Quadrature Encoder input (2 pins)
    • 2 PWM outputs
    • 6 GPIOs
    • CLK input to PRU1 is also broken out for experimental synchronous captures with BeagleLogic

    Work on the layout will begin soon.

    Here's a link to the PDF of the schematic.

  • Schematic 80% complete

    Kumar, Abhishek07/12/2017 at 16:27 0 comments

    BeagleLogic Standalone schematic capture is now 80% completed. The following components/features have been placed:

    • Logic Analyzer frontend
    • OSD3358 supporting circuit
    • Gigabit PHY (Microchip KSZ9031) and Ethernet Port
    • USB Ports
    • SPI Flash
    • SD Card slot and eMMC
    • RTC

    The following components are to be placed:

    • Expansion header containing UART, SPI, I2C and PWM ports
    • Serial Debug Connector
    • Some additional GPIOs

    You can view the partially completed schematic at this link.

  • Kernel module ported to Linux v4.9

    Kumar, Abhishek07/02/2017 at 10:45 0 comments

    When the kernel for BeagleLogic was initially written in 2014, it was based on the 3.8.13 kernel that featured first-class support for device tree overlays and BeagleBone capes.

    The cape manager disappeared in later kernel versions, only to reappear in kernel version 4.0 and above. However the API for controlling the PRUs had changed too much and it made BeagleLogic incompatible with those kernel versions. Thus BeagleLogic had to stick to the 3.8.13 kernel version, even though nicer things were happening in future kernel versions.

    The API for the PRUs became stable enough starting with kernel version 4.4 (there were official TI examples) so that I could look at porting BeagleLogic to this version. Ultimately, by end of May I sat down and rewrote parts of the PRU firmware (GitHub link to commit history) and by mid-June the kernel module was ready. I was advised to use the 4.9 kernel instead of 4.4 I was originally planning to port it to, and as a result it is up-to-date with the latest TI kernel as of now. It's already submitted to and included in the BeagleBoard's kernel repository (4.9 branch).

    I hope that keeping it in sync with upcoming kernel releases will be easier and something I will actively do for BeagleLogic.

View all 10 project logs

  • 1
    Build the Board (or buy one!)

    As the component count is large, it would be a better idea to get the board assembled or buy one than hand assemble it.

  • 2
    Plug in the board to your PC

    Also Install drivers for Ethernet over USB, if on Windows.

  • 3
    Open http://beaglebone.local:4000/

    This opens the BeagleLogic web interface. Click the buttons and start sampling!

View all 3 instructions

Enjoy this project?



Adam Vadala-Roth wrote 08/02/2017 at 02:24 point

congrats on best product!

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Kumar, Abhishek wrote 08/02/2017 at 04:05 point

Thank you!

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kelu124 wrote 07/21/2017 at 06:29 point

hi Abhishek, I'd be keen on trying to get an add-on board for the standalone board. I need high speed daq and have played interestingly with a raspberry one to reach 24Msps  Reading this bbb standalone board makes me think to do a high speed adc board. Reaching, and streaming as you mention 100msps at 8 bit (or just getting 2 channels, or one at 16bit, but not streaming it) would definitely be of interest to me. Let's keep in touch, and let me know when you release prototypes :)

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x893 wrote 07/19/2017 at 19:04 point


What ~ cost of all components with PCB ?

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Michael Welling wrote 07/07/2017 at 02:51 point

Let me know if you need a design review.

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Kumar, Abhishek wrote 07/12/2017 at 07:30 point

Thanks! I will get back to you.

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kelu124 wrote 07/02/2017 at 21:20 point


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Kumar, Abhishek wrote 07/12/2017 at 07:30 point


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oshpark wrote 07/02/2017 at 19:26 point

This is a great idea!

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Kumar, Abhishek wrote 07/12/2017 at 07:30 point


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BeagleBoard Foundation wrote 07/02/2017 at 19:25 point

Very exciting!

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Kumar, Abhishek wrote 07/12/2017 at 07:30 point


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