Well, well, well.... after all the testing and planning, the first revision of the DDL4-CPU assembly is complete and ready for further testing! During the assembly and testing, I've already identified more than a dozen places for improvement, fixes and optimizations! The most notable of these is how the conditional jump with Carry Flag, and Zero Flag will be implemented (more on that soon!). However for now, there is a lot of testing that needs to be done before the next set of boards get ordered!
Well, at 244 components, the Mega-One-8-One, is a mega PITA to assemble by hand, but it's done none the less. The Mega-One-8-One is a gate level replica of the 74181 Arithmetic Logic Unit (ALU), which was previously highlighted on hackaday.com ( Huge 74181 is a classic ALU you can actually understand!). Since the 74181 is not available new any more (yes you can get New Old Stock or NOS), I decided to build a replica for use in the DDL4-CPU so that the math and logic functions could be more easily understood. I originally had pins on the pcb near each input and output LED, but this didn't really lend itself to interfacing into a project, so I made a second revision of the design which included a 1x22 0.1" header that allows for the quick interface to the rest of the DDL4-CPU design...
Well, after a seriously hard week of debugging some new hardware at $DAYJOB, I was able to crack open a beer, and start assembling the Mega-One-8-One for the DDL4-CPU! I've populated all the capacitors, the current limiting resistors for the LEDs, and the LEDS. To make everything fit, I used 0603 resistors, caps and LEDs for the Mega-One-8-One. The caps and resistors aren't too much of an issue as they are not polarity/orientation sensitive, but the LEDs need to place with the correct Anode/Cathode alignment. I usually can do 0603 LEDs without an issue, as the bottom of the LED has some markers to indicate orientation for the Cathode. After placement, I use my multimeter on the diode setting to step through all the LEDs to make sure they are all placed with the correct orientation.... ugh this board has a LOT of components!
It has been over a decade since the last time I needed to program a parallel (E)EPROM of any type. Back in those days there was a parallel port on virtually every laptop and desktop computer. I ended up selling my old parallel port programmer years ago on ebay. With the build of the DDL4-CPU, it was time for me to look for something a little more modern. A quick search turned up the TL866 usb based programmer. Further searching revealed that there was a linux command line tool created for these programmers. So I ordered one! Well, I didn't read carefully enough.... there are three variations of the TL866 available, two are compatible, the third is not! The TL866 II+, is a slightly newer version that supports a wider range of voltages and has more In-System-Programming (ISP) support. So this was the one I selected to start with. The device works fine with the provided windows software, but no support available in the linux software for the TL866 II+. I ordered a second unit, this time the TL866CS (the TL866A would have worked as well). After downloading a copy of the linux tool, I was able to read and write to the EEPROM that I had selected. The linux tool did warn that the firmware on my device was old and I needed to update it. Unfortunately, the linux tool doesn't offer the capability of doing the firmware update (or none that I could find), so I ended up digging out an old windows laptop that keep around for just such occasions (I purchased it at a pawn shop for $99 - the wifi doesn't work!). After downloading the software and installing it, I flashed the new firmware, and went back to my linux setup with no more warnings! Sweet little setup!
UPDATE: someone shared the link to a linux based firmware updater!
Before I began the layout of the DDL4-CPU, I came up with an initial Instruction Set Architecture (ISA) for the design. It went through several revisions as I was designing the boards and refined the components. Here at the last minute as I am programming the EEPROMs, I decided to make a few last minute changes. I am using a 4-bit opcode with a 4-bit immediate. I've also allowed for in the design to have 2-byte commands. I only plan to implement the 2-byte commands with the conditional jump commands with this revision. This is mainly to work out the details of how it should work. It was a challenge to come up with an optimal configuration. I reviewed a lot of third party designs including the TD4 cpu described in the Japanese language book "How to Build a CPU" by Iku Watanabe. A good English description of the book and contents can be found at the "Building a 4-Bit CPU" web page. You can also find a number of attempts at building a TD4 cpu on hackaday.io pages!
So now that I have enough modules assembled to do some testing, I programmed the ROM with a series of test patterns to exercise the program counter, the OP Code Register, and the Immediate Data Register. The first 16 bytes of the ROM are programmed with 0 to F in the upper nibble which corresponds to the OP Code. The second set of 16 bytes of the ROM are programmed with 0 to F in the lower nibble which corresponds to the Immediate Data. The third set of 16 bytes, have both the OP Code nibble and the Immediate Data nibble programmed from 0 to F. This pattern helps identify any LSB/MSB signal swaps as well as make sure the ROM is reporting data from the correct address. In this video, I run the test first at 2Hz clock, reset the board, and then run at the 10Hz clock. At the end of the video, I demonstrate using the "step" button to pulse the system clock. So far things are looking good!
With the completion of the Registers Module, the only remaining board is the Mega-One-8-One ALU !!!! Then I can begin doing some incremental testing and programming of the EEPROMs for decode as well as programming the ROM for some test data....
The assembly of the Registers Module is complete! The Registers Module started off as the ALU Module as part of the 4-Bit Architecture Experiments project. The ALU portion has been removed, leaving the A, B and Accumulator registers. Another 4-bit latch has been added to handle the ALU flags. Only two flags are currently being stored, but I was already using the 74LVC173D 4-bit latches for the A, B, and Accumulator registers, and it makes sense that in the future I might want to have additional flags. Each register has LEDs to indicate the contents and a LED to indicate when the register is enabled.
Well.... I have six of the modules completed! The Registers Module is next on the assembly list. It is pretty straight forward assembly and is based mostly on the ALU module from the 4-Bit Architecture Experiments project. I removed the ALU portions from the board and replaced them with a 4-bit latch to hold the resulting arithmetic flags from the Mega-One-8-One ALU. The ALU portion of this project is the most tedious to assemble. The last prototype I assembled took three evenings to complete. There is nothing complicated about the board, there are just a LOT of components that need to be correct....
I have to admit using a CPLD for the I/O Module feels like a bit of a cheat, but I already had this design completed as part of the Digital Design Doohickey project. I hope to replace this with something more appropriate later on down the road. The design includes some LEDs for display the data that is currently being presented on the 4-bit Data Bus. The CPLD is directly connected via the I/O pins to a 7-segment display, 4 LEDs, 4 switches, and a push button. The CPLD is programmed via a 2x5 JTAG header on the board. The Altera EPM7064SLC44-10N is a costly part (around $9.00USD at digikey), and is a End-of-Life project. I already had some on hand, and the board was already designed, so I decided to use it for now. The design is loosely based around a post made on a Hackaday a while back called "A Better Way to Plug a CPLD Into a Breadboard".