Shared Silicon

Description

I had one semi-successful tapeout in 2015 (it was not 100% success because chip was slow). I have a library of CMOS 0.5um components that was designed by me in Magic and I want to share it with others (and I use extreme form of open source here - namely "public domain") with hope that others will share silicon with me on my next tapeouts to reduce price for each of us. I offer manufacturing of 40 silicon dies packaged in DIP40 ceramic package and each die could be divided up to 4 parts and each part could be occupied by separate project with separate power (to prevent short-circuit in one part to kill whole chip). Dies could be packaged differently, but for now assumption is everything must be DIP40 and each participant will get proportional amount of chips (if you occupy 25% of the die then you get only 10 chips). Because all participants will see all designs everything must be open source - no proprietary or patented parts are allowed! For business entities only!!!

Details

Results of my 1st tapeout received on October 20th, 2015:

Initially it was 8 packaged and 32 unpackaged chips:

Later I packaged all unpackaged dies and got 3 different packages for the same die - DIP40, DIP28 and SOIC16:

Chip itself is 3 separate test projects on one silicon die:

Each test project is a collection of CMOS circuits to test basic building blocks for binary, ternary and quaternary logic. Work was done in conjunction with a stealth hardware start-up that will reveal more details soon...

Magic VLSI layout open source tool: http://opencircuitdesign.com/magic/

Technology files for Magic: http://opencircuitdesign.com/magic/tech.html

We use SCN3M.35 technology (0.5um lambda=0.35).

To run Magic with this technology files:

magic -T SCN3M.35

Below you can see very helpful Magic tutorial from Youtube user CellRider:

Files

nedocon-cmoslib.zip

Alpha-version of open source CMOS library of IC building blocks with models for LTSpice and layouts for Magic (kind of silicon proven for 0.5um)

Zip Archive - 676.95 kB - 10/03/2016 at 03:52

Download

Project Logs

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Estimation of area for ternary selector
SHAOS • 12/17/2017 at 03:05 • 0 comments

In order to calculate how heavy TRIASIC could be with current limitations let's estimate how compact a ternary selector could be using our library of gates. If you paid attention to this project then you probably remember that ternary selector (multiplexer/demultiplexer) on 1st chip was implemented from binary gates manifesting analog behavior as showed below:

This is how it looked in "spread" form (large squares are "filler cells" that do nothing):

So one ternary selector has:

3-input NAND gates: 2
3-input NOR gates: 2
2-input NOR gates: 1
NOT gates: 6
Transmission gates: 3

TG and NOT gates are "low-profile" gates that could be only 53 units high and 3-input gates have 64-unit height. We can arrange elements in 2 rows - NOT and TG in one row and NAND/NOR in another row.

Width of elements:

3-input NAND gate - 38 units
3-input NOR gate - 38 units
2-input NOR gate - 30 units
NOT gate - 22 units
Transmission gate - 29 units

1st row (NOT and TG): 6*22+3*29=219 units wide and 53 units high
2nd row (NAND and NOR): 4*38+30=182 units wide and 64 units high
Between rows we will have 7+7+3=18 units for 2 metal interconnects, so total height will be 53+64+18=135 units (47um) and total width 219 units (77um) - this is 20 modules from side to side horizontally and vertically we can put 25 rows of such modules (if we allocate space between them for 5 metal lines of interconnects) or totally 20*25=500 ternary selectors.

And at the end one more picture from that 1st chip ;)
NAND ASIC
SHAOS • 12/10/2017 at 08:27 • 0 comments

I have an idea of "NAND ASIC" in 2x2 mm when on chip itself we only have 2-input NAND gates and metal layers do interconnects between those NAND gates to implement something as NEDONAND in silicon :)

Let's count how many gates we may have - 1 gate occupies 30x57 units (lambdas) that is 10.5x20 um:

We have 2000x2000 um area where we will put pads and power rings so available area will be about 1550x1550 um. NAND gates may be arranged in the rows one after another like this:

So in 1 row we may put 147 2-input NAND gates. Then we may have a number of horizontal lines in metal layer 1 or 2 after each row for interconnect - every line will take 3 lambdas for spacing and 4 lambdas for metal itself, so it's 7 lambdas per line plus additional 3 lambdas per spacing between next row of NAND gates. Let's calculates how many gates we may put on single chip if we will have N metal lines between rows of NAND gates:

N=3 : interconnect will take 3*7+3=24 lambdas or 8.4um so height of every row will be 28.4um and on the chip we may have 1550/28.4=54 rows or 147*54=7938 NAND gates

N=5: 5*7+3=38 lamdas or 13.3 um so 33.3 um for row, 1550/33.3=46 rows or 147*46=6762 NAND gates

N=7: 7*7+3=52 lamdas or 18.2 um, 38.2 um for row, 40 rows or 147*40=5880 NAND gates

N=9: 9*7+3=66 or 23.1 um, 43.1 um for row, 36 rows or 5292 NAND gates

I'm still not sure how many interconnection lines will be good enough for most designs - probably I need to "synthesize" something 1st to see how it will go...

P.S. Next step - to design compact layout for ternary multiplexer/demultiplexer ( see https://hackaday.io/project/11779/log/47306-useful-outcome ) to make ternary ASIC prototype as well (half of the chip might be binary NAND-ASIC prototype with for example NEDONAND implemented and another half - ternary TRI-ASIC prototype with for example parts of TRIADOR implemented ; )
Planning next "tapeout"
SHAOS • 12/02/2017 at 04:03 • 5 comments
According to this page:
https://www.mosis.com/db/pubf/fsched?ORG=ON-SEMI
in 2018 MOSIS will collect C5F/C5N 0.5um designs on these dates:
- April 2nd
- August 6th
- December 3rd
So we can choose April 2nd, 2018 as possible next "tapeout" date for our 2nd chip - anybody interested? ;)

Maximal possible size of the die for minimal cost is 4 mm^2 now (it could be square 2x2 mm or 2000x2000 um) and we will order minimal possible quantity - 40. Planned packaging was DIP40, so die may have 40 pads on it (10 pads on each side of the die). Our old pad generator will not work, because last time die had slightly bigger size - 2.2x2.2mm (to meet 5mm^2 limit at that time).

Technically possible to put more pads - if we will keep the same sizes and spacing as last time (100x100um pads with 50um between each other and 25um from pads to border - actually it was recommended size by MOSIS) then we can put N*150 on each side and for 2000um it will be N=13, so it's 13+13+11+11=48 max and now, surprise-surprise, DIP48 is also available as an option for packaging (even though slightly more expensive)!

Now I plan to have everything OPEN SOURCE and fully available on every stage of the work under PUBLIC DOMAIN :)
Useful outcome
SHAOS • 10/09/2016 at 15:49 • 0 comments

As I said before my 1st chip is a collection of test circuits for binary, ternary and quaternary building blocks. One of that building blocks could be used directly even right now - it is ternary selector (that could connect 1 pin to any other 3 using 1-wire ternary control). SOIC16 package has only this building block wired to pins with this pinouts:
Pin 1 - Vss (negative voltage)
Pin 2 - MUST BE GROUNDED (Vss)
Pin 3 - S (analog input "select")
Pin 4 - N (analog input/output "negative")
Pin 5 - O (analog input/output "neutral")
Pin 6 - P (analog input/output "positive")
Pin 7 - C (analog output/input "common")
Pin 8 - Vdd (positive voltage)
Pin 9 - MUST BE GROUNDED (Vss)
Pin 10 - NOT CONNECTED
Pin 11 - NOT CONNECTED
Pin 12 - NOT CONNECTED
Pin 13 - NOT CONNECTED
Pin 14 - NOT CONNECTED
Pin 15 - NOT CONNECTED
Pin 16 - Vss (negative voltage)
I designed a break-out board to convert SOIC to SIP (breadboard friendly):
It's working pretty well (except the fact that switching frequency is limited to 20 kHz):
Oscillograms if selector connected as ternary buffer (N = -5V, O = 0V, P = +5V):
Oscillograms if selector connected as ternary inverter (N = +5V, O = 0V, P = -5V):
And below you can see respective SPICE simulations generated by ngspce on model extracted from final chip layout (with models of PMOS and NMOS transistors for chosen CMOS technology found on Internet):

Schematics of this selector:
Above ternary circuit is based on regular binary blocks described before - NOT, NAND, NOR and TG. Here I use effect of shifting of threshold of NAND and NOR binary gates if all or some inputs connected together (LTspiceIV simulation):
As you can see there are gaps between active zones (kind of "break-before-make" non-shorting transition) to prevent switches (X12,X13,X14) to be ON simultaneously while moving between zones (and it may cause short circuits between power lines because any of pins N,O,P could be connected to most positive or most negative voltage to implement some ternary functions using this universal ternary selector).
Filling cell
SHAOS • 10/07/2016 at 04:00 • 0 comments

Manufacturing required to fill all empty spaces by some filling cells that have metal layers and poly to meet density rule - this should support all neighboring designs. I created this cell 10x10um with 3 metal layers and poly layer connected to each other:
This is how CIF-viewer showed this (and how it looks on actual silicon - with "fingers"):
Problem is (and I think it's main reason of chips slowness) there is no connection to the ground (P-substrate here)! So chip is having a lot of floating capacitors between signals and ground that eat all dynamic - it has to be fixed before 2nd tapeout...

Pads generator

SHAOS • 10/04/2016 at 19:49 • 10 comments

This simple straightforward script generates 40 pads (each 100x100um) and power rings (VDD & VSS) for 2.2x2.2mm CMOS 0.5um design (silicon proven in 2015):

# Generating DIP40 pads and VDD/VSS rings for SCN3M 0.5um process
# This script is PUBLIC DOMAIN - use it on your own risk!
rm -f pad.* pads.*
magic  -T SCN3M.35 -dnull -noconsole << EOF
drc off
box position 0 0
box size 100um 100um
paint pad
label IO
save pad
cif
erase
cellname rename pad pads
# Pads
box position 2085um  980um
getcell pad
box position 2085um 1130um
getcell pad
box position 2085um 1280um
getcell pad
box position 2085um 1430um
getcell pad
box position 2085um 1580um
getcell pad
box position 2085um 1730um
getcell pad
box position 1730um 2085um
getcell pad
box position 1580um 2085um
getcell pad
box position 1430um 2085um
getcell pad
box position 1280um 2085um
getcell pad
box position 1130um 2085um
getcell pad
box position  980um 2085um
getcell pad
box position  830um 2085um
getcell pad
box position  680um 2085um
getcell pad
box position  530um 2085um
getcell pad
box position  380um 2085um
getcell pad
box position   25um 1730um
getcell pad
box position   25um 1580um
getcell pad
box position   25um 1430um
getcell pad
box position   25um 1280um
getcell pad
box position   25um 1130um
getcell pad
box position   25um  980um
getcell pad
box position   25um  830um
getcell pad
box position   25um  680um
getcell pad
box position   25um  530um
getcell pad
box position   25um  380um
getcell pad
box position  380um   25um
getcell pad
box position  530um   25um
getcell pad
box position  680um   25um
getcell pad
box position  830um   25um
getcell pad
box position  980um   25um
getcell pad
box position 1130um   25um
getcell pad
box position 1280um   25um
getcell pad
box position 1430um   25um
getcell pad
box position 1580um   25um
getcell pad
box position 1730um   25um
getcell pad
box position 2085um  380um
getcell pad
box position 2085um  530um
getcell pad
box position 2085um  680um
getcell pad
box position 2085um  830um
getcell pad
# Corner markers
box size 50um 50um
box position 0 0
paint psc
box position 2160um 0
paint psc
box position 2160um 2160um
paint psc
box position 0 2160um
paint psc
# Ground ring
box position 175um 175um
box size 1860um 1860um
paint m1
box position 180um 180um
box size 1850um 1850um
paint psc
box position 195um 195um
box size 1820um 1820um
erase
paint m1
box position 178um 178um
box size 20um 20um
erase
paint m1
box position 180um 180um
box size 15um 15um
paint psc
box position 2012um 2012um
box size 20um 20um
erase
paint m1
box position 2015um 2015um
box size 15um 15um
paint psc
paint m1
box position 178um 2012um
box size 20um 20um
erase
paint m1
box position 180um 2015um
box size 15um 15um
paint psc
paint m1
box position 2012um 178um
box size 20um 20um
erase
paint m1
box position 2015um 180um
box size 15um 15um
paint psc
box position 200um 200um
box size 1810um 1810um
erase
# Power ring
box position 210um 210um
box size 1790um 1790um
paint nw
paint m1
box position 215um 215um
box size 1780um 1780um
paint nsc
box position 225um 225um
box size 1760um 1760um
erase
paint nw
paint m1
box position 213um 213um
box size 15um 15um
erase
paint nw
paint m1
box position 215um 215um
box size 10um 10um
paint nsc
box position 1982um 1982um
box size 15um 15um
erase
paint nw
paint m1
box position 1985um 1985um
box size 10um 10um
paint nsc
box position 213um 1982um
box size 15um 15um
erase
paint nw
paint m1
box position 215um 1985um
box size 10um 10um
paint nsc
box position 1982um 213um
box size 15um 15um
erase
paint nw
paint m1
box position 1985um 215um
box size 10um 10um
paint nsc
box position 230um 230um
box size 1750um 1750um
erase
save pads
cif
quit -noprompt
EOF

Result is pads.mag file (and pads.cif just in case) that looks like this:

CMOS transmission gate
SHAOS • 10/03/2016 at 04:20 • 0 comments

LTSpiceIV model:
Test circuit for LTSPiceIV:
Magic layout:
CMOS NOR gate
SHAOS • 10/03/2016 at 04:15 • 0 comments

LTSpiceIV model:
Voltage transfer curve:
When both inputs change state together threshold shifts left (blue line).
Magic layout:
3-input version:
LTSpiceIV for it:
CMOS NAND gate
SHAOS • 10/03/2016 at 04:10 • 0 comments

LTSpiceIV model:
Voltage transfer curve:
When inputs both changed state threshold shifts right (blue line).
Magic layout:
3-input version (also presented in the archive):
and LTSpiceIV model for NAND3:
CMOS inverter
SHAOS • 10/03/2016 at 04:03 • 0 comments

LTSpiceIV model:
Voltage transfer curve:
Magic layout for 0.5um CMOS:

View all 10 project logs

Discussions

Yann Guidon / YGDES wrote 10/22/2016 at 20:59

I still can't join this project :-(

Are you sure? yes | no

SHAOS wrote 10/22/2016 at 23:53

You're still invisible :(

Are you sure? yes | no

David Anders wrote 10/09/2016 at 03:26

this is great! i was already looking at some broker houses for fab shops! the idea of using a die with Chip-On-Board(CoB) sounds perfect for this!

Are you sure? yes | no

SHAOS wrote 10/10/2016 at 02:43

For CoB I need to buy a bonding machine (and it is not so easy)

Are you sure? yes | no

Yann Guidon / YGDES wrote 10/10/2016 at 13:08

but that's the way to go ! :-D

Are you sure? yes | no

SHAOS wrote 10/10/2016 at 13:47

Eventually - yes

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Yann Guidon / YGDES wrote 10/05/2016 at 01:31

You also need to design distributed on-die capacitors for better power supply decoupling... This could also help a little with your speed issues. All that unused space could have been turned into an energy storage...

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SHAOS wrote 10/05/2016 at 01:40

Capacitors (and resistors) on silicon are also gonna be huge and take space...

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Yann Guidon / YGDES wrote 10/05/2016 at 08:11

But you have left a lot of space unused.

Are you sure? yes | no

SHAOS wrote 10/05/2016 at 12:11

My next tape-out will be fully occupied ;)

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Yann Guidon / YGDES wrote 10/06/2016 at 06:59

Did you just start the "Occupy Silicon" movement ? :-P

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SHAOS wrote 10/06/2016 at 11:59

Yeah :)

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Yann Guidon / YGDES wrote 10/04/2016 at 00:38

One obvious and direct application will be to redesign the #Yet Another (Discrete) Clock in this CMOS technology. I'm already imagining how it would be possible to translate the 10TFF :-D

Are you sure? yes | no

SHAOS wrote 10/05/2016 at 01:41

I think a lot of projects here on Hackaday may be easily translated into this :)

Are you sure? yes | no

Yann Guidon / YGDES wrote 10/03/2016 at 23:38

Pro-tip : Concerning your gates library, think about creating mirrored and rotated versions in every possible combination, to reduce wire length and ease routing ;-)

Are you sure? yes | no

SHAOS wrote 10/03/2016 at 23:45

I read somewhere that all transistors in CMOS must be oriented exactly the same way because of some feature of silicon, so idea is all blocks are having the same height and could be arranged in the row where top is positive power and bottom is negative power (ground). Between rows I have channels for 5 horizontal metal lines for forward and backwards connections. Vertical connections could be done in 3rd metal layer that can go over transistors with no problems.

Are you sure? yes | no

Yann Guidon / YGDES wrote 10/03/2016 at 23:50

The transistor orientation must be related to "strained silicon" which is probably not a feature at your 500nm node...

then you need to get the information from the foundry about the straining orientation.

BTW if you alternate Vdd and Vss, you can alternate/miror the gates instead of wasting the tiny space between them. You have at least miroring in X and Y so 4 versions of the gate, which could be automated somehow...

I should hack a JAvascript manual place&router ;-) JSfloorplan for the win !

omg did I just start another project ?

Are you sure? yes | no

SHAOS wrote 10/04/2016 at 00:10

I have design in "Scalable CMOS" rules which are "foundry-agnostic" so theoretically it could be downgraded as low as 180nm if needed (but I still think it will require some serious modifications).

Are you sure? yes | no

Yann Guidon / YGDES wrote 10/04/2016 at 00:19

Yup, the standard rules taught in schools :-)

I'd like to review your layout one day. And I'll examine your cell library as well. 15 years ago, I fought to go to a university where they developped their own "open source" cell lib...

Are you sure? yes | no

Yann Guidon / YGDES wrote 10/03/2016 at 19:49

The unpacking video is so ... tense ! You are really extremely excited !

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SHAOS wrote 10/03/2016 at 22:50

of course - it was 1st time :)

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Yann Guidon / YGDES wrote 10/03/2016 at 22:56

i understand !!!!!

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Ted Yapo wrote 10/03/2016 at 17:37

This is an amazing idea, a significant step beyond multi-project wafers. I wonder if it would be possible to multiplex the pins like the PIC's peripheral-pin-select so that designs can share pins - it seems like this could easily become the limiting factor. I could imagine a config register interface that you could write to switch the pins between designs.

Do you have an idea for the approximate cost?

Are you sure? yes | no

Yann Guidon / YGDES wrote 10/03/2016 at 17:45

I have thought about this multiplexing thing, too. I'm in favor but the methodology is probably not yet mature enough.

I/O pins and memory seem to me to be the most limiting factors but it's an excellent sandbox !!!

The cost would be in the range of a few K$ / design but this also depends on what process node is selected for the whole run. 0.5µ is too large and slow, I'd try 0.18 or 0.13µ... But Alex wants things that work at 5V :-/

Are you sure? yes | no

SHAOS wrote 10/03/2016 at 17:58

and 0.5um is cheaper (but 0.35um is close and only a little cheaper if you order more items).

0.13 and 0.18 are more expensive (like x2)

Are you sure? yes | no

Yann Guidon / YGDES wrote 10/04/2016 at 00:16

I'd go for .35µ. Twice the gate density so larger SRAM arrays. How many metal layers ?

I'd also investigate why your design was slow. I'm not a guru but must have at least one or two clues of what could go wrong.

Are you sure? yes | no

SHAOS wrote 10/04/2016 at 00:29

3 metal layers - standard C5 process. It's for 5V, but it's working pretty well up to 20V (and down to 3.5V). I think my problem was filling cell that I came up with (foundry required all empty space filled with something to support neighboring areas) - it looks like it created a lot of parasitic capacitance between signals (and the ground) that ate all dynamic of the circuit...

Are you sure? yes | no

Yann Guidon / YGDES wrote 10/04/2016 at 00:33

I noticed you have a lot of empty space...

Are you sure? yes | no

SHAOS wrote 10/04/2016 at 00:38

it's not empty, it's filled with filling cell...

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Yann Guidon / YGDES wrote 10/04/2016 at 00:42

I mean "empty" as in "not used", "there's quite a lot of space to populate with operating stuff" :-)

Are you sure? yes | no

SHAOS wrote 10/04/2016 at 01:00

for now yes - it is not so much to test yet, so lets stick with 0.5um ;-)

Are you sure? yes | no

SHAOS wrote 10/03/2016 at 22:49

yes, I multiplexed pins already for bottom-left design (through network of transmission gates) - problem is power lines will be shared in this case, so short circuit in one design may kill whole project

about cost - manufacturer has confidential prices, but anybody can request automatic quote from them and get actual number for the whole DIP40 prototype manufacturing

Are you sure? yes | no

Yann Guidon / YGDES wrote 10/04/2016 at 00:21

Note about multiplexing...

it's a good idea but not ideal.

Now, if you have your own bonding machine, you *could* create way more pads but only populate those required by one particular project. Think about it ! ;-)

Are you sure? yes | no

SHAOS wrote 10/04/2016 at 00:35

Pads are huge and occupy space where a lot of transistors could be located, so it's always tradeoff between number of pads and useful area of the silicon...

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Yann Guidon / YGDES wrote 10/04/2016 at 00:41

Yup. OTOH your first run is "almost empty" :-P

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SHAOS wrote 10/04/2016 at 01:02

first run was intended to be packaged by them into DIP40, so there are only 40 pads on the sides (in accordance to their spec).

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Yann Guidon / YGDES wrote 10/03/2016 at 17:36

Oh and we should get a bonding machine !

Are you sure? yes | no

SHAOS wrote 10/03/2016 at 17:54

yes, it should reduce cost of prototyping (up to $50 per chip).

Are you sure? yes | no

Yann Guidon / YGDES wrote 10/03/2016 at 22:51

I'll let you find it. I've blown away my equipiment budget for this decade.

Are you sure? yes | no

SHAOS wrote 10/03/2016 at 22:54

I found a few used bonders online for not so scary price, but I still can't find source for empty DIP packages...

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Yann Guidon / YGDES wrote 10/03/2016 at 23:28

The trick is to bond directly to PCB... CoB-like: "chip on board", like in watches, multimeters and other cheap gadgets with a black epoxy blob.

Cheap...

Are you sure? yes | no

SHAOS wrote 10/03/2016 at 23:34

yes, it's doable, but - under "epoxy blob" it could be anything - FPGA, CPLD or even MCU - and haters may say that it is not true full custom :)

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Ted Yapo wrote 10/03/2016 at 23:52

I bet you could come up with a package design from a few layers of PCB epoxied together that emulated a DIP package pretty well. Three layers might do it - a bottom layer to bond the die to, a middle layer with a central cutout and a ring of pads for bond wire connections, and a top layer with a larger cutout to protect the wires.

Are you sure? yes | no

SHAOS wrote 10/04/2016 at 00:02

Pseudo DIP? May be

Are you sure? yes | no

K.C. Lee wrote 10/04/2016 at 00:09

You already need to have make a PCB, might as well go a bit beyond. Simply mount a bare die directly (aka black blob) on a breakout PCB. Decoupling caps, other needed parts and your breakout connectors can be mounted where it is needed.

Are you sure? yes | no

Yann Guidon / YGDES wrote 10/04/2016 at 00:22

@Ted Yapo I love your idea !

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SHAOS wrote 10/04/2016 at 00:36

@K.C. Lee it's true

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Yann Guidon / YGDES wrote 10/03/2016 at 09:03

Awesome !
That will be one great way to test #AMBAP: A Modest Bitslice Architecture Proposal :-D

Are you sure? yes | no

SHAOS wrote 10/03/2016 at 17:53

and #NEDONAND homebrew computer :-)

Are you sure? yes | no

Shared Silicon

Description

Details

Files

nedocon-cmoslib.zip

Project Logs

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Estimation of area for ternary selector

NAND ASIC

Planning next "tapeout"

Useful outcome

Filling cell

Pads generator

CMOS transmission gate

CMOS NOR gate

CMOS NAND gate

CMOS inverter

Discussions

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