I can't keep track of all the awesome "discrete" CPU designs on my own project. There is a list of such projects but it is "curated". Why not make my own list and invite like-minded hackers ?
If you have a similar project here, drop me a message and I'll add you to the contributors.
For practical reasons (it's impossible to list everything on the 'net), the "project" is mostly about gathering people from HaD who built their CPU (or at least digital electronic devices). Here are some external links for those who just can't get enough:
Lately I was looking for very fast diodes to design faster DTL/TTL discrete gates.
silicon epitaxial diodes can be quite fast but still have a limited frequency of rectification (particularly the cheap ones).
As noted by @K.C. Lee on #YGREC-ECL : "Carrier mobility isn't as good as electrons. That's why NPN, N-MOSFET have better performance than their PNP, P-MOSFET counterparts." so a complementary TTL gates, with a PNP input stage, would probably be speed-limited by the input transistors.
The recovery time makes a difference in several designs including switching power supplies. If you dig into the physics, there is a usually a trade-off between several other parameters and recovery time. Just to give you an idea, the datasheet for a BAT42 Schottky diode says the reverse recovery time at 10mA is no more than 5 ns."
Rectification speed was already a burning subject in the 40s because it was essential to the war effort (faster diodes means higher carrier frequencies, shorter wavelengths and better radar resolution)
ECL prevents all these issues because
there are only NPN transistors
no diode (no recovery time)
However there are more transistors... so maybe DCTL is an interesting alternative ?
@Yann Guidon / YGDESasked me to do a write-up of the Direct Coupled Transistor Logic (DCTL) of the famous CDC 6600 computer. When it was released, and for some years, the CDC 6600 was one of the fastest and most powerful computers in the world. When we take a look at the logic family that it used, it will be obvious to see why:
It uses very few components, primarily transistors, with no diodes
The transistors which perform the logic are driven very hard, to the point where the quality of the transistor fabrication actually matters a great deal
The logic levels are dangerously close together (in the 6600’s case “0” = 0.2V, and “1” = 1.2V).
The cacading and interlinked circuits must be carefully “tuned” input and output impedances MUST agree precisely, or the logic will not function due to noise or otherwise.
The Basic Unit: The Inverter
There are primarily two main articles available online which deal with the electronic description of DCTL logic. The first is the following:
James B. Angell, “Direct-Coupled Logic Circuitry” (1958) Proceedings of the Western Joint Computer Conference: Contrasts in Computers, 22-27.
This is not a great deal. On Bitsavers, there is no folder for the engineering documents of the 6600, as opposed to the 1406, and 3600-series CDC logic, which I also aim to cover because it is a very interesting high-speed DTL.
So bear in mind that the information I am presenting here is limited, and if you want to build your own DCTL circuits you are most likely going to have to design your own, because there are no complete design documents online for the 6600 which you would have been able to copy and modify.
Anyway here is the basic building block of DCTL:
The CDC 6600’s inverter:
The 1950s DCTL inverter:
By the time the 6600 was built, transistor fabrication had developed and improved markedly. In fact the first few pages of the chapter of the CDC-published book on the digital electronics of the 6600’s DCTL go on about how the new silicon transistors they used in ‘69/‘70 made the 6600 possible. So this explains why the 6600 uses NPNs, as opposed to the older implementation using PNPs.
As you can see, you would be forgiven for mistaking DCTL with Resistor-Transistor Logic (RTL) if you had only an inverter to look at. I agree with the speculation on the (tiny) Wikipedia article on DCTL that it evolved from RTL.
Obviously the thought process that lead to developing this logic family was “what if we had RTL but got rid of all the resistors?” The point of having resistors in RTL is to allow you to increase the voltage margins of the logic levels. It also allows you to better control the flow of current throughout the circuitry and match the impedances of the inputs and outputs.
The first problem you have with DCTL is – how do you make sure you can switch transistors without driving them too far into saturation? The solution is to use transistors with special impedances and gain ratios.
Take a look at the special transistor characteristics that the conference proceeding document outlines:
This is obviously based on an old understanding of exactly how well-designed transistors are, but you can see we’re only switching very small amounts of current, and the V(BE) of the operation of the transistors when in saturation/conduction is far lower than your standard BC548/9 or 2N3904/6.
I haven’t checked yet, but I believe transistors with these kinds of characteristics should be able to be obtained cheaply. The maximum switching time required in this specification from the 1950s is easily obtained with modern...
(note : the ideal current is about 4mA per gate and the oscillator reaches 307MHz on breadboard)
On the other hand, Complementary Transistor Logic is a bit like DTL but the input diode is replaced by a PNP. This greatly increases the input impedance and helps with many things. Operating voltage and current might be significantly lower, it even reduces the transistors count by 2 compared to ECL. But if it's easy to get one sort of FAST transistors, the complementary type might not be easy, as cheap or as fast... I have only stocked one type of germanium (PNP, because Ge NPN is rare) and silicon (well, I have mostly NPN, some PNP but i have no idea how to find a PNP equivalent of BFS480...
(as usual, the 2 diodes in series could be replaced by a red LED ?)
The BC857 has a high gain so the input current can be very low and this reduces fanin/fanout issues. The speedup capacitor might need some tuning, maybe 1 or 2nF ? And the resistors could be reduced to increase current and speed.
I've also read mentions of hysteresis of CTL gates, due maybe to capacitance, which can reduce the operating speed. A Schottky diode might be needed to remove bias buildup... or even add a resistor in parallel with the speedup capacitor ? Or what about simply avoiding the voltage shift by using more power rails ?
Another parameter is : sometimes, using better and faster transistors simply lets the gate run faster. But it can come at a high price so topology is still critical...
Now, the only way to compare is to try, right ?
(repost courtesy of @Dana Myers ) Just for the sake of discussion, Fairchild had their own TTL family back in the day when the 74-series was not an industry standard (or Fairchild had their "74F" series). They did TR, TD and TT : transistor-resistor logic, transistor-diode logic and here transistor-transistor logic. The datasheet shows no Baker clamp, but R5 might have helped...
Okay! We’ve had a look at the Diode-Transistor Logic of the DEC R-Series Logic, but that isn’t the only electronic logic system that was employed in building discrete discrete component computers. As I explained in the post on R-Series logic, back in 2013 it was some IBM computer which implemented an exotic electronic logic system which lead me to go down the “popular” DTL path. I will continue my investigation into different logic systems in this post with the IBM Standard Modular System (SMS) logic. IBM SMS logic doesn’t just implement specific systems of logic families, but also whole different logic families! The IBM SMS uses what is now known as Emitter-Coupled Logic (ECL), as well at Resistor-Transistor (RTL) logic and DTL. ECL is a very difficult logic family, and RTL is unpopular in hacker circles, so we will look at the IBM SMS DTL logic implementation first, and then just look at their ECL circuits. The Don Lancaster RTL Cookbook is sufficient really for people who wish to build discrete component RTL computers.
IBM Standard Modular System Diode-Transistor Logic
I have obtained the electronic description of the different IBM logic implementations from the IBM Transistor Component Circuits volume of the Customer Engineering Manual of Instruction. You can find this manual easily by searching the above words on the internet. There are also manuals describing the exact electronic schematics of the flip-chip cards used in IBM mainframes such as the 7070 and the 7090. They’re worth a look if you want some inspiration for solving a particular concrete problem.
The SMS DTL system uses four different logic levels. They are divided into two fundamental kinds, “T” line levels and “U” line levels.
As you can see, positive T levels swing from -0.7V to 6.0V, whereas negative T levels swing from 1.4V to -6.0V. Positive U levels go from 0V to -7.4V, and negative U levels move from -5.3V to -12V. There are schematics in the Transistor Component Circuits manual for how to convert T and U lines to each other. They’re not worth mentioning here because we don’t need to get into that much detail.
The Fundamental Gates
Below you can find the schematic for the fundamental positive-logic NAND gate, or negative-logic NOR gate. IBM doesn’t use the standard terminology for these gates, probably because the manuals for this system were written in the late-50s early-60s, before the terminology settled to what we know today. You’ll also notice that the symbols for transistors here are also non-standard by contemporary wisdom. The same reason should apply here. We won’t concern ourselves here with the physical electronic characteristics of the transistors and the diodes. I’ll put some work into that later.
There are three gates specified here. As you can see:
It is possible to interface the output of a DTL gate into ECL gates.
The first gate (at the top) takes a +U logic level and outputs a -T logic level.
The second gate (Gate “A”) takes a +U input and outputs a +T logic level.
The third gate (Gate “B”) is similar to the first one: it recieves a +U level, and outputs a -T level, as well as being able to interface with ECL gates.
It is possible to take T-line inputs and output U-line logic:
These gates can drive ECL gates as well! Note well that the T-line inputs for the above gates are NEGATIVE T line levels (-T levels).
There are other inverters specified in this manual, such as “Power Inverters”, which drive bigger loads and have bigger gate fan-outs. You can peruse the manual to look at those at your leisure.
There are also emitter-follower gates, which amplify the current of signals. There are also circuits for driving indicators connected to T and U line signals.
Below you can find the schematic for a basic IBM SMS flip-flop:
Hello! This is Blair Vidakovich. I was recently given entry into the hackaday TTLers group! I have tried many times, unsuccessfully, to create a discrete component computer. My basic logic element was a NAND gate, and I was using a popular form of DTL logic unit. I was copying the same electronic schematic as the Tiny Tim DTL computer. You can find the research and build log for this abandoned project here: (http://www.northdownfarm.co.uk/rory/tim/tinytim.htm). Anyway this was my basic logic element, the NAND on the far right.
I got stuck trying to build a ring counter, which I suppose I would use for control signals. I now see that a ring counter was not necessary, because many TTLers have gotten away with functioning discrete component computers without ring counters. In fact many people have successfully built four-phase clocks, so I now don't really need to worry at all, because the problem has been solved for me!
The reason why I got stuck was because I was attempting to build a DTL edge-triggered D flip-flop, and no matter how I tried, I could not build one that contained SET and RESET terminals. I could build one with just a clock and an INPUT terminal, but I could not go any further:
Enter the Discrete-Component PDP-8
I started researching and building a discrete component CPU/computer when I was diagnosed with schizophrenia in July 2013. The level of detail and concentration you have to come to master prevented me from getting any more delusional. I gave up the project when I started my PhD in 2015. I made another attempt to make a four-phase clock in 2016, but I failed again.
Then when I returned to this project a month ago (Feb 2018), I remembered I came across some schematics for an old discrete-component IBM computer back in 2013, but balked at the idea of using their basic logic element because it used so many bizarre voltages. "It used negative voltages!" I thought. There was no way I was going to be able to manage a project with such whacky logic levels, like negative voltages for positive logic signals. I went down the TTL logic route for five years.
This time, in 2018, I was determined to get further. I knew discrete component computers were built in the 50s and 60s, and I knew they were able to generate clock signals and have multi-phase clocks. All I had to do was find their schematics.
So I did. I found a wealth of resources on the DEC PDP-8. It is a wonderful computer architecture. It has a single accumulator you use with something like 6502 zero-page memory addressing in order to perform calculations. It is very RISC-like with a tiny number of opcodes, and it only contains something like 500-odd gates. So in February I thought it would be a wonderful computer to clone.
...if only I had enough money.
When I found out I could join this TTLers group, I decided I wanted to share my research on the strange DTL architecture of the PDP-8 in the hope it would help somebody.
The Standard Logic Pulse of the PDP-8
Before I start describing the electrical and logical system of the PDP-8, I want to explain how I came to obtain all this information. I retrieved it from pdp8online.org. Virtually the entire library of information required in order to repair, construct or just simply understand the PDP-8, as well as other DEC minicomputers, is all online at that website.
All of the information I have explained here comes from the DEC 1967 Digital Logic Handbook. It is the last digital logic handbook that uses R-series logic. From 1968 onwards, DEC uses M-series logic, which is basically just normal TTL.
Anyway here is the standard logic pulse of the PDP-8.
The PDP-8 uses DEC's proprietary R-series logic. As the following diagrams explain, R-series logic takes a -3V signal to be a digital ONE,...
RAM is one big problem for "discrete projects". It must be fast, large and cost-effective. There are many types of discrete RAM but none that is based on discrete MOSFET (yet).
Integrated DRAM uses MOSFETs but they differ from the discrete form because of the intrinsic diode with the substrate : it takes two discrete MOSFET to make one normal MOSFET. This would not be cost-effective to use discrete MOSFET to implement classic DRAM circuits.
I found inspiration with the diode-capacitor cell described for the TIM computers :
I can't figure out what capacitance was used in the relay-based TIM8. However, with a MOSET-based circuit, the capacitance can be greatly reduced (to 100nF for example) because the required trigger energy is considerably lower. I even have a reel of dual Schottky diodes in SOT23. But I'm not sure about the leakage...
Now, a good MOSFET has a pretty low leakage. I have played around (on paper) and have come up with a topology that replaces the diode with a MOSFET. The gate capacitance is not used but the parasitic diode is !
Each access cycle takes 2 steps:
Read and empty the storage capacitor: drive RD high => This pushes the capacitor's lower electrode high, which is then read on the Data line. Probably a threshold current is required to read a "1".
Write the value: drive the desired level on the Data line, drive RD to 0V and WR to 1 (let the current flow to RD so the lower electrode is 0V).
It's funny that the read phase works a bit like a charge pump...
Data, RD and WR are totem-pole (complementary) drivers. I will have to try different circuits for the sense. The line and column select (demultiplexers) will need a lot of transistors too... But at least it's more compact than the only other MOSFET RAM that I know :-)
Now I wonder what should be the refresh frequency...