07/12/2020 at 05:37 •
Recently, I have been working with the iCE40UP5K FPGA on my Xosera video project for the rosco_m68k. My main development board for this project has been the iCEBreaker FPGA board from 1BitSquared (which is an excellent board). However, I also wanted to support a lower cost, smaller board that might be more suitable for "embedding" in the video project, so I was also planning to support the Upduino FPGA board that uses the same FPGA (which is fully supported by the open-source FPGA toolchain).
Frustratingly, I found that my design which worked fine on the iCEBreaker wasn't working at all on the Upduino (with appropriate I/O pin changes etc.). After some debugging, I determined that the PLL was having issues (the "PLL lock" signal would not stay on reliably indicating the PLL was "not happy"). A short time after discovering this issue I found this article on the (current) Upduino 2.1 maker's blog which seemed to explain my trouble: Ground trampolines and Phase Locked Loops (basically design flaws in the Upduino 2.x board keep the PLL from operating reliably).
The original Upduino 1.0 board was pretty amazing when it came out for $9.99, however it had some issues with how it was shipped and it was inconvenient to use (with no JTAG or external oscillator) and also poor electrical design. A while later, the design was updated to the Upduino 2.0 which had FTDI JTAG (and 12Mhz oscillator) added and a few other features. This was a nice improvement, but apparently this board also had a very poor electrical design (rumored to be designed by a student).
While hanging out on the rosco_m68k Discord, working on my video project Xosera, I met another 68K and FPGA enthusiast Claude. We had some discussions about FPGA video, and the Upduino FPGA board and it's issues (he was aware of the PLL issues and had improved his board with some "user modifications"). He was also playing around with some FPGA video projects and posted an amazing DVI hack he did on Twitter showing the iCE40UP5K directly outputting DVI video using an Upduino 2.0 FPGA board. This was enough to get the attention of the current Upduno 2.1 maker
Venkat took over the Upduino project from the creator and has been selling the Upduino 2.1 on Tindie (which was however, using the same flawed 2.0 electrical design). When he first took over, he sent an invite to buyers inviting them to fill out a survey to see how Upduino could be improved in an upcoming version. He seems to have done everything possible to accommodate everyones wishes where possible with Upduino 3.0 (as well as addressing the underlying electrical design issues).
Copying from the Upduino 3.0 GitHub wiki and Tindie page, here are some improvements over Upduino 2.x:
- Lattice UltraPlus ICE40UP5K FPGA with 5.3K LUTs, 1Mb SPRAM, 120Kb DPRAM, 8 Multipliers
- 4 layer board, solid ground plane, dedicated power layer for 3.3V and 1.2V distribution
- All FPGA pins including LED driver pins are brought to 0.1" headers
- Any optional bridges must be done using special bridge-type footprint instead of resistors to make modification easy
- All passives to be no smaller than 0603 footprint
- Fix silkscreen so its easy to read, add Pb Free, WEEE symbol, "Made in USA"
- Move Micro USB connector inboard a little bit to allow clean depanelization
- Open source schematic and layout using KiCAD design tools
- Dedicated power and ground planes
- Minimum of 10uF bulk capacitance on all power rails: USB, 3.3V, 1.2V
- Dedicated decoupling capacitance on each FPGA pin placed close the FPGA pin
- Power decoupling per FTDI recommendations (using ferrite beads)
- Change LDO's to be smaller parts, capable of 200mA max output
- Oscillator: ...
07/05/2020 at 22:57 •
With some extra "stay at home" time on my hands, I was looking around for a retro project to work on (and have some fun by learning something). While I enjoy 8-bit CPUs and there are a lot of great 8-bit 6502 and Z-80 (and other) retro system projects on HaD and around the Internet, I haven't seen as many 16-bit ones - especially 68000 family. However, one that did catch my eye was the rosco_m68k project by @Ross Bamford.
I have a lot of affection for the 68000 microprocessor family, going back a long time. I think it started way back when I read this 1980 Kilobaud Microcomputing magazine article about "16-bit Super Processors" (and even as a kid reading this, the 68000 seemed "clearly superior" to me). I also had the good fortune to have a preliminary edition of the "Motorola 68000 16-bit Microprocessor User's Manual" (with the black cover) "fall into my hands" in 1980 - which turned out to be somewhat life-changing (during a car ride from a friends father, who owned an early computer company, he had a copy lying on the back seat next to me - and when I asked about it, he gave it to me). I studied that manual for years and learned a lot about the 68000 and computers in general before I ever got my hands on an actual 68K CPU (the first was a 68008 card for an Apple II, but then later on I was an early Amiga developer etc.).
So far it has been a fun experience. Within the first week or so of hanging out on the rosco_m68k Discord chat server (while waiting for my kit to arrive) there were several good discussions. In fact, one discussion has led me to start my own little hardware project for use with rosco_m68k ("Xosera" - I'll have more on that with a project post soon).
When my rosco_m68k kit arrived, I found it to be straightforward and enjoyable to assemble. Ross has done a nice job making it easy (and he has been good about "tweaking" things based on feedback, so I found it pretty "smooth"). Since I was a bit too impatient to get started, I didn't even notice the link to his instructions (and it still was no problem - with PCB clearly marked, a "chip map", labelled chips where needed and even labelled resistors - so no need for "color-code" decoding). It booted up for me on the "first-try".
For fun, I ported an old version of the Drystone benchmark to rosco_m68k (and the hard part there was mostly getting GCC to compile the ancient C code, not the rosco_m68k). Rosco looks pretty good when benchmarked next to other classic 68k machines (and I hear rumors of a blazing 10MHz...).
At this point my rosco_m68k system has grown a bit, with SD card storage (and development firmware for it), a backplane and 4MB RAM expansion (so 5MB total). I also have a V9958 VDP video board kit on its way as I write this.
Pretty soon, it looks like I'll be ready to write a little 68k game or "demoscene" demo. 😅