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Kobold K2 - RISC TTL Computer

A 16 bit RISC computer with video display, from just a few TTL and memory chips.

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The Kobold K2 CPU will be on a single pcb, constructed from TTL IC's.

Its main characteristics are:
- 16 bit processor, 16 bit databus
- 8 registers
- can access one Megabyte of memory
- no microcode
- every instruction executes in two cycles


To make it a complete computer, the K2 CPU will be connected to a mainboard, that will have:

- memory
- video system, 80 x 25 characters text
- video system, full color graphic mode with two layers
- sound
- onboard mass storage 32MByte
- I/O connectors

Constraints are:
- low number of parts (TTL)
- no of-the-shelf processor or microcontroller
- no 74181 ALU

For the CPU part, around 40 TTL IC's will be used.

MOTIVATION

After having worked several months on the first Kobold CPU , I got the feeling that it was going in the wrong direction. I was working on a Javascript assembler, and got tangled up in the microcode complexity. I also didn't like that so many parts were needed to decode the microcode. So I decided to make a huge change in the design. Here is Kobold K2 !

So what will change ?
  - Microcode is not used any more, instructions will be RISC
  - Four new 16-bit data registers in hardware (now total 8 registers)
  - The 8-bit ALU will change to 16-bit ALU
  - All instructions need two cycles (fetch, execute) 

The Kobold K2 will be almost twice as fast, and its operation will be easier to explain.
The video system will stay almost the same.


STRATEGY

Finding the balance between low number of parts and high functionality is one of the key aspects of TTL CPU design. I want to keep the part count low, but not to the extreme as in #1 Square Inch TTL CPU. The CPU part of the computer should fit on a single PCB.

To keep the control system simple, every instruction should execute in a single cycle. If the ALU was kept 8 bits wide, that would mean 2 instructions for many 16-bit actions (as in the Z80 or 6502), and that would slow down 16-bit operations. Therefore, the ALU is now 16 bit wide. I don't want to use the 74181 ALU, so to keep part count reasonable, the ALU has only a few instructions.  The low number of instructions also simplifies control.

LOGS

1. Operation principle

2. Instruction set

3. Accessing memory

4. Instruction sequencing

5. Subroutines

6. Instruction encoding and conditional branching

7. Schematic of the CPU

Adobe Portable Document Format - 73.74 kB - 09/19/2019 at 17:49

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  • Schematic of the CPU

    roelha day ago 0 comments

    What you have all been waiting for....

    The first version of the schematic for the CPU was just uploaded to the file section !

    A few things were added:

    • Provision for reading and writing bytes from/to memory. Address bit A0 will select low or high byte (as with most processors). Writing bytes will need software assistance. 
    • The 64-word Zero page has got companion of another 64-word zero page. The second zero page is called the vector page, and is automatically selected whenever zero-page contents is written to the PC or WP register. This is ment to be used for frequently accessed subroutines. A call can get its address from the zero page, saving space for an immediate value in the program code.

    The connectors of the CPU will probably change.

    Explanation of schematic will be done in a next log.

    Number of chips grew slightly above 40, would you believe it is 42 ?  Finally we will know the question: "What is the number of TTL IC's in the KOBOLD K2 CPU ?".

    [ edit: schematic updated today, 20190919 ]

  • Instruction encoding and conditional branching

    roelh2 days ago 0 comments

    At the moment, this is the instruction encoding:

    You get a bigger version when you click on it.

    An instruction is 16 bits. The upper 8 bits are in the left part of the picture, and the lower 8 bits are in the right part. The upper 4 bits control almost directly the data path, and the other bits set displacement and register numbers.

    CONDITIONAL BRANCHING

    The CPU only supports branching on carry set. To be more precise, EVERY ADD instruction will do a branch on carry.

    The branch must be within the same instruction block, and the branch target is the next slot as defined in NNN, but with the highest bit set to one.

    So what if we don't want to branch at all ? Then we put the next instruction in a slot with a number higher than 3. If now the carry gets set, it will make the highest bit of the next slot number one. But it is already one, so it will go to the same instruction, whatever the carry bit may be.

    And what if we want to branch on NO-carry ? We simple change the positions of 'normal' next instruction and the jump target. This is possible, because instructions can be in any position within a block.

    Note that jump-on-carry can also be used to test for zero. Just add 0xFFFF to the value that you want to test. If there is a carry, the value was not zero. The constant 0xFFFF will not cost us space for an immediate variable if we put it in the zero page space.

  • Subroutines

    roelh5 days ago 0 comments

    This is the instruction sequence for subroutines:
    • In slot 2, save the program counter to the D3 register
    • In slot 3, load the program counter with the subroutine address (found in slot6, shown in GREEN)
    • The subroutine is executed now. The first instruction saves the return address, that was stored in D3, in the workspace at slot 15.
    • When the subroutine has finished, the program counter is loaded with the saved program counter and execution continues at slot 7 in the main program.
    • Back in the main program, instruction 4 is executed, followed by instruction 6 and then a jump to the next block. 

    By convention, the slot to return to is always slot 7.

    In most cases (but not in this example), the subroutine will also create its own "stack frame" by using a new value for the workspace pointer WP. This makes nested and recursive functions easy.

    In this example, the call instruction is in slot 2 and 3. But it can of course also be placed in other slots. Note that this mechanism utilizes the possibility to put instructions in any order that you want. 

    ADDRESSING WITHIN 256K RETURN LOCATIONS WITH ONLY 16 BITS 

    The program counter has 16 bits, where bit zero is always 0 because instructions are only on even addresses. Each value in the PC addresses a sequence of 8 instructions. So the maximum number of instructions that can be addressed is 262144. 

    For the return address, only 16 bits have to be stored. The drawback is that within an 8-instruction block there can only be one subroutine call, because the return point is always in slot 7. 

    So there is no "near or far" madness in CALL and RETURN instructions. Return addresses are just a single 16 bit word (instead of two 16 bit words). This makes calling and jumping faster and saves memory space. 

  • Instruction sequencing

    roelh5 days ago 0 comments

    WARNING: The addressing and sequencing of instructions in Kobold K2 is rather unusual.

    In the previous log I stated that the program counter uses the object model. A simple picture will make this clear:

    This shows how the program counter points to a block of eight instructions (This could be a block of sixteen instructions, but for various reasons eight is used). We call these eight instruction positions 'slots'.

    Every instruction is 16 bits wide.

    All the instructions will be executed, and then the CPU will continue with a next block of instructions. How ?

    Within every instruction, the lowest three bits contain the slot number of the following instruction that must be executed (indicated in RED). It acts as a kind of counter. In the seventh slot, the slot number of the following instruction is 0 again. But the instruction in that slot increments the PC, so  the CPU will continue with the next block of instructions. The PC-increment is just a regular CPU instruction. No extra hardware needed for that. (Note that the PC must be incremented by 2 each time, because instructions are at word addresses.)

    This makes it easy to support immediate operands. The instruction that uses an immediate operand, specifies the PC as pointer and uses the slot number (here: 7)  as displacement:

    Several instructions in the same block can have an immediate operand, as long as you use a different slot number for every immediate value.

    Get used to all the tricks that can be done ! For instance, there is no need to put the instructions in sequence:

    In this example, the first four instructions are placed in the first four slot numbers. But at instruction 3, the instruction tells us that the following instruction is in slot 7 ! 

    So instruction number four is in slot 7. The following instructions are placed in preceding slots. The last one is placed in slot 4.

    Actually, you can place instructions in any order that you want, as long as each instruction points to the next one. (But by convention, the first instruction is in slot 0.)

  • Accessing memory

    roelh5 days ago 0 comments

    This 16 bit processor has a 20 bit address bus. How is this address generated ?

    Around 40 years ago, developers of the Intel 8086 were facing the same problem. This time, we will use an easier solution. But I doubt if my solution will be more succesful.

    TWO MEMORY MODELS

    In the Kobold K2, memory can be accessed with two different models:

    MODEL 1

    In the linear model, each address register has its own page register. A page register can be written with a MOVP instruction. 

    The memory address consists of bit 0-15 coming from the address register and bit 16-19 coming from the corresponding page register.

    In instructions that reference memory, the displacement should be set to zero when this model is used.

    MODEL 2

    In the object model, the page register of an address register is not used (and it should be set to zero). In this case, bit 16-19 of the address come from the 4-bit displacement value in the instruction.

    In C terms, the address register can contain a pointer to 64K different structure instances. Each structure has a maximum of 16 word-sized members. The instruction can specify which member is addressed. This supports the "->" operator in a single instruction.

    HOW IS DETERMINED WHICH MODEL IS USED ?

    This is the nice part. There is no mode switch. At every memory access, the page register of the used address register is bitwise OR'ed with the displacement value in the instruction. 

    So when the page register is zero, the displacement determines the address. And when the displacement is zero, the page register determines the address. You could of course use a non-zero value for both. That might be useful in some situations.

    So it is up to the programmer to decide which address register is used in which mode. 

    But for the PC (program counter ) and WP (workspace pointer), the object model is normally used.

  • Instruction set

    roelh6 days ago 0 comments

    This is the envisioned instruction set. It is not complete, several instructions have to be added.

    Several things that are possible, are not in the overview. For instance, there is no INC for a data register but it can be incremented by adding #1 to it. Logical OR and AND are possible by combination of CPL and NOR instructions. 

    For subtracting, one of the operands must be complemented (CPL) and then incremented (INC) to obtain the 2-complement, and then both operands must be added (ADD). There is a ADDI (add and increment) available, so the INC and ADD can be a single instruction.

    A jump is a MOV to the program counter (A0). To do a call, you must store the programcounter (in a data register) and then do a jump (exact call system to be discussed later).

  • Operation principle

    roelh09/12/2019 at 09:40 0 comments

    CPU BLOCK DIAGRAM

    Main parts are:

    • 4 data registers D0 - D3 (16 bit)
    • 4 address registers  A0 - A3 (20 bit)
    • 16 bit ALU that can do only ADD, MOV and NOR
    • shift unit that can shift one position to the right
    • instruction register
    • Single memory for program and data

    Every instruction needs two cycles:

    EXECUTE CYCLE

    This will let the ALU calculate a new value and put this in the shift unit. Or it will store a data register in memory.

    The inputs for the ALU are:

      • a data register and a memory operand, or
      • a data register and an address register

    For memory operands, the address comes from an address register and displacement, or it is a zero-page address.  Immediate operands can be selected by using the program counter as address register (and using a displacement).

    FETCH CYCLE

    The contents of the shift unit is transferred to the destination register. The contents can be either shifted or unshifted. The PC (address register A0) is connected to the memory address. The next instruction is fetched from memory and is put in the  instruction register.

    Incrementing the PC will be discussed later.

    DATA FLOW FOR MAIN INSTRUCTION TYPES

    This shows how data from memory is added to a data register. 

    The ALU can also do a MOV or NOR operation. By making combinations, the following functions can be obtained:

    • LOAD: The ALU can transfer the memory data to a register without change.
    • CPL: A register can be complemented by NOR'ing it with the value #0.
    • SUBTRACT: Complement one of the operands. Then do the ADD and finally ADD #1.
    • OR: Do a NOR followed by complement-register
    • AND: First complement both operands, then do NOR 

    The same instructions can be done when the operand comes from an address register instead of from memory. The displacement value (part of instruction word) is not used here. This opens the possibility to use these bits to enable other functions, like shifting or add-with-carry.

    Finally, storing a data register is straightforward. There might be separate instructions for store-word and store-byte.

    Several topics will be discussed later:

    • incrementing the PC
    • conditional branches
    • carry handling
    • subroutines
    • loading the upper 4 bits of address registers

    I can already uncover a bit more by showing my nice drawing:

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Discussions

threeme3 wrote 6 days ago point

Roel, very interesting development again.

Just curious about the PC increment, looking to your drawing something very smart is happening there I think. Just guessing, is it that during the fetch cycle the current PC is incremented by the ALU (with one one of the values in the data registers) and  written back in A0?

Guido

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roelh wrote 6 days ago point

The PC increment system is very unusual. I will soon write a log about it.

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Dave's Dev Lab wrote 6 days ago point

how are you planning to implement the VGA support?

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roelh wrote 6 days ago point

This will be similar to the first Kobold. But interrupts are difficult in the new design, so I plan to use a DMA system where the video system stops the CPU to obtain access to the shared RAM. So the CPU will only run during blanking time.

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Chase Rayfield wrote 2 days ago point

How about double clocking the ram and interleaving CPU and VIDEO accesses? I guess it depends on how fast the system clock is and how fast you ram is... even if only part of your ram used faster chips this might still make sense.

  Are you sure? yes | no

roelh wrote 2 days ago point

Hi Chase, video will have to read two 8-bit pixels from memory every 80nS, and I don't think I will succeed making a 40nS cycle for video and a 40nS cycle for the CPU. But the CPU could run almost continuously if video got its own independent memory, or if only characters are read and an independent character ROM is used.

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Dan Maloney wrote 09/12/2019 at 14:54 point

Love these discrete chip CPU builds, especially TTL - I cut my teeth on those chips. Looking forward to seeing more progress!

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