#AMBAP: A Modest Bitslice Architecture Proposal was meant to be a discussion about a bitslice-oriented architecture, not an almost-complete relay computer, so I moved it here!
So far, the features are:
- 16-bits datapath made of 16 identical "processing" boards (each is one "bitslice") with a) register set b) ALU c) data memory
- About 2500 relays :
- 500 for the RAM,
- 500 for the register set,
- 500 for ALU,
- 500 for instruction fetch and decoding,
- another 500 for I/O...
- Expected speed : about 20 instructions per second (very RISC style so "instruction" means ROP2, ADD/SUB/CMP or single-bit shift). To be determined and confirmed. The memory arrays might be the slowest part (again).
- 256 words of DRAM, made of 8Ki capacitors (and 16Ki diodes). The refresh circuit uses memory cycles when the processor does not access the Data Memory Bus.
- Uses РЭС15 (low-voltage russian SPDT relays) with the specially-developed CC-PBRL topology (Capacitive-Coupled Pre-Biased Relay Logic) with 3.3V and 12V domains. This enables higher power-efficiency and lower ripple on the power supplies.
- Power supplies are symmetrical : 0/12V/24V for the high-fanout signals, and 0V/3.3V/6.6V for the simpler logic parts. Relays are great at jumping from one power domain to another :-) The higher voltage is usually less loaded and requires a smaller power supply but more decoupling for the transients.
- Display through a (memory-mapped) Flip-Dots Luminator matrix. You can spy the activity in real time and see the stack as it updates, for example. Or play Tetris or #Game of Life bit-parallel algorithm.
- Programming model / ISA : 8 registers, including 4 "normal" registers and 2 pairs of "address/data" for register-mapped memory access. It's a very basic RISC architecture without the load-store part. Like ARM there is a small shifter in front of the ALU.
- Programming : using diode ROM, either soldered or with DIP switches... Several programmable cards should be built.
- PC is separate and (unlike #YASEP Yet Another Small Embedded Processor) requires dedicated JUMP instructions (not considered or evaluated yet).
- I/O through an expansion board and explicit instructions (later, one day). Or might be memory mapped, who knows.
The instruction format is not defined yet.