YGREC16 - YG's 16bits Relay Electric Computer

Fork of #AMBAP, here I discuss about the physical implementation of the bitslice architecture with russian РЭС15 (see what I did here?)

Similar projects worth following
The AMBAP project ( ) has diverged too much from architectural exporation to low-level prototyping.
"AMBAP" is the name of a proposed architecture that has proved to be fruitful. Now, I have found a suitable name for the relay implementation so it's time to spin it off into a project on its own.

#AMBAP: A Modest Bitslice Architecture Proposal was meant to be a discussion about a bitslice-oriented architecture, not an almost-complete relay computer, so I moved it here!

So far, the features are:

  • 16-bits datapath made of 16 identical "processing" boards (each is one "bitslice") with a) register set b) ALU c) data memory
  • About 2500 relays :
    • 500 for the RAM,
    • 500 for the register set,
    • 500 for ALU,
    • 500 for instruction fetch and decoding,
    • another 500 for I/O...
  • Expected speed : about 20 instructions per second (very RISC style so "instruction" means ROP2, ADD/SUB/CMP or single-bit shift). To be determined and confirmed. The memory arrays might be the slowest part (again).
  • 256 words of DRAM, made of 8Ki capacitors (and 16Ki diodes). The refresh circuit uses memory cycles when the processor does not access the Data Memory Bus.
  • Uses РЭС15 (low-voltage russian SPDT relays) with the specially-developed CC-PBRL topology (Capacitive-Coupled Pre-Biased Relay Logic) with 3.3V and 12V domains. This enables higher power-efficiency and lower ripple on the power supplies.
  • Power supplies are symmetrical : 0/12V/24V for the high-fanout signals, and 0V/3.3V/6.6V for the simpler logic parts. Relays are great at jumping from one power domain to another :-) The higher voltage is usually less loaded and requires a smaller power supply but more decoupling for the transients.
  • Display through a (memory-mapped) Flip-Dots Luminator matrix. You can spy the activity in real time and see the stack as it updates, for example. Or play Tetris or #Game of Life bit-parallel algorithm.
  • Programming model / ISA : 8 registers, including 4 "normal" registers and 2 pairs of "address/data" for register-mapped memory access. It's a very basic RISC architecture without the load-store part. Like ARM there is a small shifter in front of the ALU.
  • Programming : using diode ROM, either soldered or with DIP switches... Several programmable cards should be built.
  • PC is separate and (unlike #YASEP Yet Another Small Embedded Processor) requires dedicated JUMP instructions (not considered or evaluated yet).
  • I/O through an expansion board and explicit instructions (later, one day). Or might be memory mapped, who knows.

The instruction format is not defined yet.

1. Capacitors and diodes
2. Clock generator
3. Dual Diodes (the hard way)


  • 2500 × РЭС15 Low voltage, russian SPDT mini-relay
  • 1 × 12V PSU
  • 1 × 24V PSU
  • 10000 × 100µF 25V electrolytic capacitors
  • 20000 × LL4148 Discrete Semiconductors / Diodes and Rectifiers

  • Dual Diodes (the hard way)

    Yann Guidon / YGDES12/18/2016 at 00:27 4 comments

    I have received "some capacitors" as well as "some diodes". The surface-mount LL4148 were meant for program wiring but the little gotcha with the DRAM made them even more important for temporary data storage.

    I have to redesign the capacitor arrays and these diodes are pretty critical because they consume a bit more of PCB real-estate. Oh and they can be very tricky to solder.

    I have chosen to save a bit of surface with a little naughty trick : solder them back-to-back, sharing a PCB pad. This saves maybe 2mm in one dimension and should not affect reliability. This means I have to redraw a new part in Eagle...

    Let's have a look at the specs of the chosen packaging (I have actually "chosen" the lowest bidder, to be honest, not minding the increased soldering efforts).

    I'm trying to determine the agreed upon miniMELF/DO35/SOD80/LL34 (pick your favorite) packaging dimensions. Most people use the 3.3-3.7mm length...

    The last screenshot shows the recommended footprint. My idea is to merge one pad with the pad of the neighbour diode. Normally, there would be at least 2×5mm but the merge saves 1.25mm, giving a length of 8.75mm. This is still quite long, longer than the capacitor's diameter. Routing will be fun.

    Another approach would be vertical soldering. Density certainly increases, as well as other kinds of headaches. I could make a tool to keep the diodes upright during soldering but the next step (connecting all the leads in the air) is less deterministic...

    Through-hole parts create their own kinds of problems. When space is constrained, the hole uses space on both PCB layers, but this area might be precious or critical on one side, for routing stakes.

    My current idea is to create a "part" in EAGLE with the capacitor and the two diodes, and rotate every other by 180° to fit everything in the 6mm grid... Hoping it will fit...

    I have DRAM capacitors (25V 100µF) both in 5×11 and 6×7mm formats. Both seem happy with 0.1" spaced through holes. That's a good starting point for the new composite part.

    So I created this symbol:

    The footprint is constrained by the size of the capacitor :

    I have chosen a grid of 6.35mm (1/4") which is a tiny bit larger than the 6mm of the previous attempt. It shouldn't be too hard to solder manually. I have given up on trying to solder the diodes back to back, the above pattern is easily integrated as an array:

    Just put the cells close to each other, snapping on the grid, and voilà.

    I have tried a 16×32 array, which is a bit larger than 10×20cm (without the mux16 and connectors). The total capacity with 16+1 slices is 512 words, or 8Ki bits, or one kilobyte. I might postpone the soldering of all the parts... Because of the "screen", initially I need maybe 64 words at first (4 columns, 1K capacitors).

    In theory, I can drive all the vertical wires of all the boards with a single 64-mux, the total relay count is therefore: 64+ (16×17)=336. Add to this the refresh logic, the data and address MUXes, the sense and buffers, and the DRAM system uses about 500 relays as expected...

    Some questions remain :

    • are there any more gotchas I have to care about ?
    • I have "solved" the partition of the MUX16, is there a solution for MUX32 ?
    • how long will the capacitors keep enough charge with the couple of diodes ? I suspect that a higher leakage will affect the refresh cycles. 512 words at 10 refresh per second (optimistic average) means that the whole array is refreshed every minute...

    This can be answered with a magic circuit called a prototype ;-)

  • Clock generator

    Yann Guidon / YGDES12/05/2016 at 01:21 2 comments

    I'm starting easily with this simple circuit that I should finalise ASAP.

    It's just another ring oscillator, with another twist. It now uses a dual power supply, capacitor coupling, and the second relay drives external signals. It's a "full" CC-PBRL system where the output's load will not disturb the frequency. It also helps a lot with the fanout.

    Then, the LFSR will be quite similar, but with an added charge pump.

  • Capacitors and diodes

    Yann Guidon / YGDES12/03/2016 at 21:57 4 comments

    In the comments of #AMBAP: A Modest Bitslice Architecture Proposal, @roelh has shown my errors with the (naive) capacitor array. Since this system is not possible, I am forced to use a couple of diodes for each capacitor. Fortunately, I had ordered a large batch for the instruction ROM...

    The system I intend to use looks like this :

    (sorry for the lousy picture, I'll take time to make a better one. Later.)

    This is different from the system used by TIM-8 but "inspired" by a paper from the early 60s that was pointed to me in some comments.

    TIM-8 differs by selecting one leg or another, for writing or reading, while I connect both to 0V, both for writing and reading. That's the "pinching" method.

    I'm pretty sure there is no loop now, since it was developped and tested long ago (according to the paper relating Bell Labs' work). But can somebody prove me wrong ?

View all 3 project logs

Enjoy this project?



Does this project spark your interest?

Become a member to follow this project and never miss any updates