01/09/2021 at 01:59 •
01/03/2021 at 00:44 •
How to generate alternate clock signals for Xilinx Artix-7 FPGA and Alchitry Au
This article started out by asking a simple question: "What if I wanted to drive my Alchitry Au FPGA design with something other than the 100Mhz master clock? " What resulted was a trip down a rabbit hole that was as distracting as it was rewarding.
If you'd like to be spared the deep-dive and get right to a concrete example, you can skip to the end for a practical introduction and come back here to understand the underpinnings of what's going on.
From the top-level documentation for the Alchitry Au FPGA, featuring the features a Xilinx XC7A35TFTG256, we know the on-board clock is 100MHz and that it can be multiplied internally by the FPGA.
- How is the master clock generated and input into the FPGA?
- How is the FPGA configured to use this particular clock input?
- How is this clock made available to other FPGA resources?
- How can other clocks be synthesized from the master clock and distributed within a design?