• Changing I2C Clock Speed [SDC] on Banana Pi BPI-M2 ZERO (Armbian)

    03/15/2023 at 01:13 0 comments

    After much searching for how to change the I2C clock speed [SDC] on Banana Pi BPI-M2 ZERO running Armbian, with a little experimentation I found a way to alter the device tree (DT) parameters to accomplish the task.  

    I've not tried other SDC clock frequencies besides 100kHz and 400kHz, so let me know if other (higher or lower) speeds work for you - your "mileage may vary".  

    This approach may also work for other platforms running Armbian, however you'll have to locate the design tree file for your specific platform - and there are many in the installation I'm using.

    It's assumed that you have already turned on I2C0 using the "armbian-config" utility.

    Your user account will need root (sudo) privileges to perform these steps:

    1. Locate the design tree file for the BPI-M2-Zero platform - typically in the /boot/dtb directory.
      cd /boot/dtb
      ls -l *m2-zero*
      -rw-r--r-- 1 root root 34592 Mar 12 20:11 sun8i-h2-plus-bananapi-m2-zero.dtb

       There are two formats of the device tree file.  DTB --> binary format.  DTS --> source (plaintext) format.  We'll want to convert the m2-zero's DTB file to plain text (DTS) so it can be edited.

    2. First, create a backup of the DTB file just in case things go horribly wrong.

      sudo cp sun8i-h2-plus-bananapi-m2-zero.dtb sun8i-h2-plus-bananapi-m2-zero.dtb.bak
    3. Next, make a DTS (editable) file from the binary.  This is done using the dtc (Device Tree Compiler) utility.  You can get help by entering "dtc --help" or consulting the manpages by entering "man dtc".

      sudo dtc -I dtb -O dts -o sun8i-h2-plus-bananapi-m2-zero.dts ./sun8i-h2-plus-bananapi-m2-zero.dtb
    4. Load up your freshly created dts file.  I'm using emacs, however you can use your favorite editor.  Nano will work as well.

       sudo emacs sun8i-h2-plus-bananapi-m2-zero.dts
    5. Search for the section that controls the I2C0 configuration.  In this case I2C0 is the one at address 1c2ac00.  How do I know that?  By having searched further in the DTS file being edited for "i2c0" and finding the corresponding address reference.   For BPI-M2-Zero in this case:
       i2c0 = "/soc/i2c@1c2ac00";

    6. If it doesn't already exist in the I2C0 control block, insert the clock-frequency parameter...

      clock-frequency = <400000>;

      ... so that it looks like the screenshot below.  So far,  I've tried both 100000kHz and 400000kHz and validated the resulting SDC frequencies using a multi-channel logic analyzer. 

    7. At this point, save the file  and exit the editor.

    8. Lastly convert the edited DTS file back to DTB format

      sudo dtc -I dts -O dtb -o sun8i-h2-plus-bananapi-m2-zero.dtb ./sun8i-h2-plus-bananapi-m2-zero.dts
    9. Finally - reboot for the changes to take effect.

      sudo reboot

    Please let me know if this solution works for you.  I'm open to being educated on other methods as well.  I'm especially interested in software control of this parameter - using IOCTL or some other means.

    Inspiration and credit where credit is due:




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    01/09/2021 at 01:59 0 comments

  • Alchitry Au - Clock Talk

    01/03/2021 at 00:44 0 comments

    How to generate alternate clock signals for Xilinx Artix-7 FPGA and Alchitry Au

    This article started out by asking a simple question: "What if I wanted to drive my Alchitry Au FPGA design with something other than the 100Mhz master clock? " What resulted was a trip down a rabbit hole that was as distracting as it was rewarding. 

    If you'd like to be spared the deep-dive and get right to a concrete example, you can skip to the end for a practical introduction and come back here to understand the underpinnings of what's going on.

    From the top-level documentation for the Alchitry Au FPGA, featuring the features a Xilinx XC7A35TFTG256, we know the on-board clock is 100MHz and that it can be multiplied internally by the FPGA.

    • How is the master clock generated and input into the FPGA?
    • How is the FPGA configured to use this particular clock input?
    • How is this clock made available to other FPGA resources?  
    • How can other clocks be synthesized from the master clock and distributed within a design?
    Read more »