• #BringAHack after Maker Faire Bay Area 2017

    14 hours ago 0 comments

    cjh-sa8vaaawubi

    Join us for #BringAHack at BJ’s after Maker Faire on May 21st!

    img_57b601538353d7.57122556_SanMateo2013

    BJ’s Restaurant & Brewhouse

    2206 Bridgepointe Pkwy, San Mateo, CA 94404

    Sunday, May 21st, 6pm to closing

    bj

    20150517_235837-animation

    laen


  • EEPROM Programmer Arduino Shield

    2 days ago 0 comments

    From the The Oddbloke Geek Blog, an EEPROM programmer shield designed for Arduino Mega:

    EEPROM_Programmer_And_Arduino_Mega.jpg

    Simple EEPROM Programmer … revisited

    Some time ago, I wrote about my DIY EEPROM programmer driven by an Arduino Mega. It’s a very simple, low-tech project … but has attracted a consistently-high number of visitors to the site and is something I use several times a week.

    http://danceswithferrets.org/geekblog/?p=765

    http://danceswithferrets.org/geekblog/?p=765

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  • Castellated Edges

    4 days ago 1 comment

    Castellations are small plated edges, typically used for making circuit boards into small PCB modules. These are often seen on wireless modules, such as the ESP8266-12E.

    While we don’t offer full support for castellations, they can be fabricated if you don’t mind a few minutes of rework and verification of the PCBs.

    Design Considerations

    It’s helpful to include a fallback hole near the edge. The ESP8266-12E boards, are a great example here. The extra via allows easy connecting of wires for rework, and makes it easy to salvage a module if the fabricated PCB doesn’t turn out perfectly.

    ESP2866-12EESP2866-12E, available at Adafruit.com

    Indicating in the design file

    Castellations are simple to call out in most design tools. Simply include a via on the PCB, so the board outline goes through it.

    However, due to our panelization process, the castellated vias must be indicated with round pads for copper and stop mask. The pads must also not extend more than 40 mil from the board edge. Square pads or pads that extend far beyond the edge will be trimmed, and the via will not be plated.

    It’s also helpful to use a 10 mil wide line for the board outline. With our milling tolerance of 5 mil, this provides a good visual indicator of where the physical board edge might be. The fabricated edge can be anywhere within that line. This is very helpful for fine-pitch castellations with smaller holes.

    Callout as seen in a design toolCallout as seen in a design tool

    Rectangular castellations can be made by using vias with round pads as noted above, and adding overlapping rectangular SMD pads. Since these pads are inside the board outline, they will not be trimmed, and will provide additional area for soldering (see below for example).

    Cleaning up the final boards

    We make a best-effort to minimize support tabs on castellated edges, but it sometimes happens. In these cases, you’ll need to file the tab off of your edge.

    Additionally, the via plating may not be fully removed during the milling process. In some cases it’s smashed next to the edge, where it can cause unwanted connectivity between vias. In others, it’s smashed inside the via, where it will prevent good solder flow. A fine point file or hobby knife will help remove excess plating.

    An unreworked castellated PCB, with visible plating stubsAn unreworked castellated PCB, with visible plating stubs Another version, with tabs on castellated edge and modifications for rectangular padsAnother version, with tabs on castellated edge and modifications for rectangular pads